Lines Matching defs:Opc
420 unsigned Opc;
423 Opc = ARM::FCONSTD;
426 Opc = ARM::FCONSTS;
430 TII.get(Opc), DestReg).addImm(Imm));
441 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
445 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
459 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
464 TII.get(Opc), ImmReg)
475 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
480 TII.get(Opc), ImmReg)
543 unsigned Opc;
549 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
551 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
553 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
572 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci;
573 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
588 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
592 MIMD, TII.get(Opc), NewDestReg)
654 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
657 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
660 TII.get(Opc), ResultReg)
832 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
834 TII.get(Opc), ResultReg)
899 unsigned Opc;
910 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
912 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
915 Opc = ARM::LDRBi12;
917 Opc = ARM::LDRSB;
930 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
932 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
934 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
946 Opc = ARM::t2LDRi8;
948 Opc = ARM::t2LDRi12;
950 Opc = ARM::LDRi12;
960 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
963 Opc = ARM::VLDRS;
975 Opc = ARM::VLDRD;
987 TII.get(Opc), ResultReg);
1048 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1049 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1051 TII.get(Opc), Res)
1322 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1326 TII.get(Opc)).addReg(AddrReg));
1554 unsigned Opc;
1555 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1557 Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1562 TII.get(Opc), ResultReg).addReg(FP));
1579 unsigned Opc;
1581 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1583 Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1589 TII.get(Opc), ResultReg).addReg(Op));
1742 unsigned Opc;
1746 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1749 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1752 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1765 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1766 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1768 TII.get(Opc), ResultReg)
1793 unsigned Opc;
1798 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1801 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1804 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1815 TII.get(Opc), ResultReg)
2634 uint32_t Opc : 16;
2640 { // ARM Opc S Shift Imm
2648 { // Thumb Opc S Shift Imm
2658 { // ARM Opc S Shift Imm
2666 { // Thumb Opc S Shift Imm
2693 unsigned Opc = ITP->Opc;
2694 assert(ARM::KILL != Opc && "Invalid table entry");
2697 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2722 unsigned Opcode = isLsl ? LSLOpc : Opc;
2780 unsigned Opc = ARM::MOVsr;
2791 Opc = ARM::MOVsi;
2799 if (Opc == ARM::MOVsr) {
2808 TII.get(Opc), ResultReg)
2811 if (Opc == ARM::MOVsi)
2813 else if (Opc == ARM::MOVsr) {
2898 uint16_t Opc[2]; // ARM, Thumb.
2932 if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2971 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
2973 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), TempReg)
2976 if (Opc == ARM::LDRcp)
2982 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
2984 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2985 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)