Lines Matching defs:MIB
562 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
590 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
594 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
596 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
598 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
600 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
604 MIB.add(MI.getOperand(OpIdx++));
607 MIB.add(MI.getOperand(OpIdx++));
608 MIB.add(MI.getOperand(OpIdx++));
635 MIB.add(AM6Offset);
648 MIB.add(MI.getOperand(OpIdx++));
649 MIB.add(MI.getOperand(OpIdx++));
656 MIB.add(MO);
659 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
660 MIB.copyImplicitOps(MI);
663 MIB.cloneMemRefs(MI);
665 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
680 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
684 MIB.add(MI.getOperand(OpIdx++));
687 MIB.add(MI.getOperand(OpIdx++));
688 MIB.add(MI.getOperand(OpIdx++));
711 MIB.add(AM6Offset);
720 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
722 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
724 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
726 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
729 MIB.add(MI.getOperand(OpIdx++));
730 MIB.add(MI.getOperand(OpIdx++));
733 MIB->addRegisterKilled(SrcReg, TRI, true);
735 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
736 MIB.copyImplicitOps(MI);
739 MIB.cloneMemRefs(MI);
741 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
757 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
779 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
781 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
783 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
785 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
789 MIB.add(MI.getOperand(OpIdx++));
792 MIB.add(MI.getOperand(OpIdx++));
793 MIB.add(MI.getOperand(OpIdx++));
796 MIB.add(MI.getOperand(OpIdx++));
806 MIB.addReg(D0, SrcFlags);
808 MIB.addReg(D1, SrcFlags);
810 MIB.addReg(D2, SrcFlags);
812 MIB.addReg(D3, SrcFlags);
815 MIB.addImm(Lane);
819 MIB.add(MI.getOperand(OpIdx++));
820 MIB.add(MI.getOperand(OpIdx++));
824 MIB.add(MO);
827 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
828 MIB.copyImplicitOps(MI);
830 MIB.cloneMemRefs(MI);
842 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
846 MIB.add(MI.getOperand(OpIdx++));
849 MIB.add(VdSrc);
856 MIB.addReg(D0);
860 MIB.add(VmSrc);
863 MIB.add(MI.getOperand(OpIdx++));
864 MIB.add(MI.getOperand(OpIdx++));
867 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
868 MIB.copyImplicitOps(MI);
870 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
880 MachineInstrBuilder MIB =
888 MIB.add(MI.getOperand(1));
889 MIB.add(predOps(ARMCC::AL));
890 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags);
891 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags);
892 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags);
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags);
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags);
897 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags);
898 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags);
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags);
903 MIB.addReg(SrcReg, RegState::Implicit);
905 MIB.copyImplicitOps(MI);
906 MIB.cloneMemRefs(MI);
1035 MachineInstrBuilder MIB =
1039 MIB.addReg(DstReg);
1040 MIB.add(Operand);
1041 MIB.add(predOps(ARMCC::AL));
1042 MIB.setMIFlags(MIFlags);
1044 MIB.getInstr()->dump(););
1880 MachineInstrBuilder MIB =
1884 MIB.addImm(0);
1885 MIB.add(predOps(ARMCC::AL));
1893 MachineInstrBuilder MIB;
1894 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
1895 MIB.addReg(AddrReg);
1897 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
1898 MIB.add(predOps(ARMCC::AL));
1917 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
1921 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
1922 MIB.add(predOps(ARMCC::AL));
1962 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1968 MIB.addReg(RegLo, Flags);
1969 MIB.addReg(RegHi, Flags);
1971 MIB.addReg(Reg.getReg(), Flags);
2015 MachineInstrBuilder MIB;
2016 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
2017 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
2018 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
2044 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
2046 addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
2047 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
2276 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
2278 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
2282 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
2288 MIB.add(predOps(ARMCC::AL));
2621 MachineInstrBuilder MIB;
2630 MIB =
2635 MIB.addImm(0);
2636 MIB.add(predOps(ARMCC::AL));
2638 MIB =
2642 MIB.add(predOps(ARMCC::AL));
2643 MIB.addReg(Reg, RegState::Kill);
2645 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2648 MIB.add(predOps(ARMCC::AL));
2649 MIB.addExternalSymbol("__aeabi_read_tp", 0);
2652 MIB.cloneMemRefs(MI);
2653 MIB.copyImplicitOps(MI);
2656 MF->moveAdditionalCallInfo(&MI, &*MIB);
2721 MachineInstrBuilder MIB =
2725 MIB.addImm(0);
2726 MIB.add(predOps(ARMCC::AL));
2729 MachineInstrBuilder MIB =
2736 MIB.add(predOps(ARMCC::AL));
2820 MachineInstrBuilder MIB =
2829 MIB.add(MI.getOperand(OpIdx++));
2832 MIB.add(MI.getOperand(OpIdx++));
2833 MIB.add(MI.getOperand(OpIdx++));
2838 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
2842 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
2843 MIB.copyImplicitOps(MI);
2844 MIB.cloneMemRefs(MI);
2851 MachineInstrBuilder MIB =
2861 MIB.add(Dst);
2864 MIB.add(MI.getOperand(OpIdx++));
2865 MIB.add(MI.getOperand(OpIdx++));
2870 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
2874 MIB->addRegisterKilled(SrcReg, TRI, true);
2876 MIB.copyImplicitOps(MI);
2877 MIB.cloneMemRefs(MI);
3223 MachineInstrBuilder MIB;
3231 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
3241 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
3243 MIB.cloneMemRefs(MI);
3245 MIB.add(MO);
3251 MachineInstrBuilder MIB =
3253 MIB.cloneMemRefs(MI);
3255 MIB.add(MI.getOperand(i));
3257 MF.moveAdditionalCallInfo(&MI, MIB.getInstr());
3259 Bundler.append(MIB);
3269 MachineInstrBuilder MIB =
3277 MIB.add(MO);
3278 MIB.add(predOps(ARMCC::AL));
3279 MIB.cloneMemRefs(MI);