Lines Matching defs:MBBI
64 MachineBasicBlock::iterator MBBI,
67 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
68 void ExpandVST(MachineBasicBlock::iterator &MBBI);
69 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
70 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
72 void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI);
74 MachineBasicBlock::iterator &MBBI);
76 MachineBasicBlock::iterator &MBBI);
78 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
82 MachineBasicBlock::iterator MBBI);
84 MachineBasicBlock::iterator MBBI,
87 MachineBasicBlock::iterator MBBI,
90 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
94 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
98 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
101 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
104 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
107 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
110 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
115 MachineBasicBlock::iterator MBBI,
552 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
553 MachineInstr &MI = *MBBI;
562 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
670 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
671 MachineInstr &MI = *MBBI;
680 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
746 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
747 MachineInstr &MI = *MBBI;
757 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
836 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
838 MachineInstr &MI = *MBBI;
842 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
873 void ARMExpandPseudo::ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI) {
874 MachineInstr &MI = *MBBI;
881 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
994 MachineBasicBlock::iterator &MBBI) {
995 MachineInstr &MI = *MBBI;
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg)
1036 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Op), DstReg)
1054 (--MBBI)->getOperand(0).setIsDead(DstIsDead);
1060 MachineBasicBlock::iterator &MBBI) {
1061 MachineInstr &MI = *MBBI;
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
1084 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg);
1091 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri))
1127 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
1139 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
1153 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
1178 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
1185 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL));
1196 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg)
1201 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M))
1243 MachineBasicBlock::iterator MBBI) {
1245 (void)determineFPRegsToClear(*MBBI, ClearRegs);
1248 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1250 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs);
1257 MachineBasicBlock::iterator MBBI,
1262 auto &RetI = *MBBI;
1279 DoneBB->splice(DoneBB->end(), &MBB, MBBI, MBB.end());
1366 MachineBasicBlock::iterator MBBI,
1368 auto &RetI = *MBBI;
1381 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1392 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS))
1403 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1406 CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
1408 CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
1413 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1421 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1430 for (const MachineOperand &Op : MBBI->operands()) {
1443 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1457 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1503 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVS))
1512 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1530 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1535 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1543 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg)
1551 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0)
1555 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1)
1561 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg)
1570 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg)
1574 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1579 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg)
1584 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR))
1589 finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator());
1594 MachineBasicBlock::iterator MBBI,
1598 bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs);
1605 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
1612 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
1627 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
1634 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1637 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP)
1646 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1649 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs);
1651 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs);
1655 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1666 for (const MachineOperand &Op : MBBI->operands()) {
1679 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD))
1693 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg)
1711 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD))
1717 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS))
1727 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1770 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
1775 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
1781 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1801 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1803 if (!definesOrUsesFPReg(*MBBI)) {
1805 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS))
1811 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM))
1818 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP)
1824 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post),
1832 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP)
1844 MachineBasicBlock::iterator MBBI,
1850 MachineInstr &MI = *MBBI;
1881 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
1976 MachineBasicBlock::iterator MBBI,
1980 MachineInstr &MI = *MBBI;
2085 MachineBasicBlock::iterator MBBI,
2088 const DebugLoc &DL = MBBI->getDebugLoc();
2091 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
2108 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
2114 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
2126 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
2129 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH))
2135 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
2147 MachineBasicBlock::iterator MBBI, int JumpReg,
2149 const DebugLoc &DL = MBBI->getDebugLoc();
2152 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2155 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R)
2160 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
2165 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP)
2174 MachineBasicBlock::iterator MBBI,
2176 MachineInstr &MI = *MBBI;
2188 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2198 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2209 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2220 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MoveOpc))
2228 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2246 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
2247 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2248 MBBI--;
2249 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2250 MBBI--;
2251 assert(MBBI->isReturn() &&
2253 unsigned RetOpcode = MBBI->getOpcode();
2254 DebugLoc dl = MBBI->getDebugLoc();
2259 MBBI = MBB.getLastNonDebugInstr();
2260 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2261 MBBI--;
2262 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2263 MBBI--;
2264 MachineOperand &JumpTarget = MBBI->getOperand(0);
2276 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
2294 BuildMI(MBB, MBBI, dl,
2299 auto NewMI = std::prev(MBBI);
2300 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
2301 NewMI->addOperand(MBBI->getOperand(i));
2309 MBB.erase(MBBI);
2311 MBBI = NewMI;
2318 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT));
2320 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI);
2324 BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
2335 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
2340 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2341 CMSEClearGPRegs(AfterBB, AfterBB.end(), MBBI->getDebugLoc(), ClearRegs,
2345 BuildMI(AfterBB, AfterBB.end(), MBBI->getDebugLoc(),
2355 DebugLoc DL = MBBI->getDebugLoc();
2356 Register JumpReg = MBBI->getOperand(0).getReg();
2364 for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse()))
2366 LiveRegs.stepBackward(*MBBI);
2368 CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs,
2372 determineGPRegsToClear(*MBBI,
2385 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg)
2394 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg)
2398 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg)
2405 CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs,
2407 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg);
2410 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr))
2419 CMSERestoreFPRegs(MBB, MBBI, DL, OriginalClearRegs); // restore FP registers
2421 CMSEPopCalleeSaves(*TII, MBB, MBBI, JumpReg, AFI->isThumb1OnlyFunction());
2430 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
2443 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2455 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2468 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
2484 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2496 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2510 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
2533 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2559 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2562 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2565 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
2581 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
2595 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2607 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
2631 BuildMI(MBB, MBBI, MI.getDebugLoc(),
2639 BuildMI(MBB, MBBI, MI.getDebugLoc(),
2645 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2666 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
2671 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
2722 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
2730 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
2760 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg)
2765 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
2771 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
2789 ExpandMOV32BitImm(MBB, MBBI);
2793 ExpandTMOV32BitImm(MBB, MBBI);
2804 ExpandTMOV32BitImm(MBB, MBBI);
2808 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
2821 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
2852 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
3011 ExpandVLD(MBBI);
3101 ExpandVST(MBBI);
3176 ExpandLaneOp(MBBI);
3179 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
3180 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
3181 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
3182 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
3188 ExpandMQQPRLoadStore(MBBI);
3193 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3197 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3201 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
3205 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
3209 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
3213 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3216 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
3226 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
3231 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
3234 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
3241 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
3270 BuildMI(MBB, MBBI, MI.getDebugLoc(),
3289 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
3290 while (MBBI != E) {
3291 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
3292 Modified |= ExpandMI(MBB, MBBI, NMBBI);
3293 MBBI = NMBBI;