Lines Matching defs:DefMCID

3343   const MCInstrDesc &DefMCID = DefMI.getDesc();
3344   if (DefMCID.hasOptionalDef()) {
3345     unsigned NumOps = DefMCID.getNumOperands();
3894                                   const MCInstrDesc &DefMCID, unsigned DefClass,
3896   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3911     switch (DefMCID.getOpcode()) {
3934                                  const MCInstrDesc &DefMCID, unsigned DefClass,
3936   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
4034     const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID,
4037   unsigned DefClass = DefMCID.getSchedClass();
4040   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
4048   switch (DefMCID.getOpcode()) {
4059     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4080     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4134       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4203                             const MCInstrDesc &DefMCID, unsigned DefAlign) {
4208     switch (DefMCID.getOpcode()) {
4233     switch (DefMCID.getOpcode()) {
4264     switch (DefMCID.getOpcode()) {
4415     unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4456       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4465   Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
4480   const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4482   if (isZeroCost(DefMCID.Opcode))
4486     return DefMCID.mayLoad() ? 3 : 1;
4490         ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4506       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4515     switch (DefMCID.getOpcode()) {
4540     switch (DefMCID.getOpcode()) {
4565     switch (DefMCID.getOpcode()) {