Lines Matching defs:CurReg

2596     MCRegister CurReg = RegClass->getRegister(CurRegEnc);
2603       RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2613     if (isCalleeSavedRegister(CurReg, CSRegs) ||
2614         MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2625     RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
5303       MCRegister CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
5304       bool CurUndef = !MI.readsRegister(CurReg, TRI);
5305       NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
5307       CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
5308       CurUndef = !MI.readsRegister(CurReg, TRI);
5309       NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
5321       CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
5322       CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5323       MIB.addReg(CurReg, getUndefRegState(CurUndef));
5325       CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
5326       CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5327       MIB.addReg(CurReg, getUndefRegState(CurUndef))