Lines Matching defs:ARMBaseInstrInfo
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
13 #include "ARMBaseInstrInfo.h"
114 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
128 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
141 ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(
163 ScheduleHazardRecognizer *ARMBaseInstrInfo::
178 ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
354 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
470 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
497 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
549 bool ARMBaseInstrInfo::
559 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
575 std::string ARMBaseInstrInfo::createMIROperandComment(
600 bool ARMBaseInstrInfo::PredicateInstruction(
634 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
660 bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,
684 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
716 return !ARMBaseInstrInfo::isCPSRDefined(*MI);
723 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
777 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
815 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
826 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
846 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
890 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1059 ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
1075 ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,
1105 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
1116 void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1316 Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1370 Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1383 void ARMBaseInstrInfo::loadRegFromStackSlot(
1573 Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1633 Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1648 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1651 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1702 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1825 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1853 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,
1877 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1964 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2031 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2061 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
2111 bool ARMBaseInstrInfo::
2137 bool ARMBaseInstrInfo::
2202 ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF,
2216 ARMBaseInstrInfo::predictBranchSizeForIfCvt(MachineInstr &MI) const {
2239 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
2272 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
2301 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
2335 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
2357 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
2489 const ARMBaseInstrInfo &TII,
2649 const ARMBaseInstrInfo &TII) {
2804 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3030 bool ARMBaseInstrInfo::optimizeCompareInstr(
3310 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
3328 bool ARMBaseInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
3725 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3779 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3893 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3933 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3967 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
4006 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
4033 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(
4379 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(
4413 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatencyImpl(
4474 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4732 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4751 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4802 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4820 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4841 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4858 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4929 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
5022 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
5058 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
5150 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
5360 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
5421 void ARMBaseInstrInfo::breakPartialRegDependency(
5454 bool ARMBaseInstrInfo::hasNOP() const {
5458 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
5472 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
5499 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
5522 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
5550 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
5556 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
5568 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
5582 ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI, Register Reg) const {
5843 ARMBaseInstrInfo::findRegisterToSaveLRTo(outliner::Candidate &C) const {
5895 ARMBaseInstrInfo::getOutliningCandidateInfo(
6116 bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI,
6219 void ARMBaseInstrInfo::mergeOutliningCandidateAttributes(
6234 bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom(
6257 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
6306 ARMBaseInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
6451 void ARMBaseInstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {
6457 void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,
6518 void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
6533 void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,
6594 void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
6607 void ARMBaseInstrInfo::buildOutlinedFrame(
6680 MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
6744 bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(
6749 bool ARMBaseInstrInfo::isReallyTriviallyReMaterializable(
6999 ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {