Lines Matching defs:Lane

68                            const DebugLoc &DL, unsigned Reg, unsigned Lane,
74                                  unsigned Lane, const TargetRegisterClass *TRC);
88                                 unsigned Lane, unsigned ToInsert);
417                                        unsigned Lane, bool QPR) {
423       .addImm(Lane)
432     const DebugLoc &DL, unsigned DReg, unsigned Lane,
439     .addReg(DReg, 0, Lane);
477     const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
485     .addImm(Lane);
542     unsigned Lane;
544       case ARM::ssub_0: Lane = 0; break;
545       case ARM::ssub_1: Lane = 1; break;
555     Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);