Lines Matching +full:0 +full:x2fc
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 let HasExtVOP3DPP = 0;
18 let HasExtDPP = 0;
31 let HasExtVOP3DPP = 0;
32 let HasExtDPP = 0;
47 let HasExtVOP3DPP = 0;
48 let HasExtDPP = 0;
52 let HasExtVOP3DPP = 0;
53 let HasExtDPP = 0;
63 let mayRaiseFPException = 0;
83 let HasSrc0Mods = 0;
132 let mayRaiseFPException = 0 in {
170 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0, AddedComplexity = 1 in {
180 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0, AddedComplexity = 1
204 let mayRaiseFPException = 0 in {
218 let mayRaiseFPException = 0 in {
230 } // End mayRaiseFPException = 0
232 let SubtargetPredicate = HasMinimum3Maximum3F32, ReadsModeReg = 0 in {
235 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
254 let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.
261 } // End mayRaiseFPException = 0
296 (i32 (V_BFE_I32_e64 i16:$src, (i32 0), (i32 0x10)))
312 let HasModifiers = 0;
401 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0,
403 (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10))))
413 // Note: 16-bit instructions produce a 0 result in the high 16-bits
433 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
474 unsigned ConstantBusUses = 0;
475 for (unsigned i = 0; i < 3; ++i) {
501 int ConstantBusUses = 0;
502 for (unsigned i = 0; i < 3; ++i) {
522 int64_t Imm = 0;
552 let HasClamp = 0;
573 let HasClamp = 0;
574 let HasSrc2 = 0;
585 HasOpSel, HasOMod, IsVOP3P, HasModifiers, HasModifiers, 0/*Src1Mods*/,
593 let HasClamp = 0;
639 let SubtargetPredicate = HasMinimum3Maximum3F16, ReadsModeReg = 0 in {
642 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
663 // V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64
664 // src0 is shifted left by 0-4 (use “0” to get ADD_U64).
668 let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,
691 (inst !if(index, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, $old, 0)
696 (inst !if(index{1}, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1,
697 !if(index{0}, SRCMODS.OP_SEL_0, 0), $old, 0)
707 foreach Index = [0, -1] in {
713 foreach Index = [0, 1, 2, 3] in {
769 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0)
792 0 /* clamp */),
804 0 /* clamp */),
812 (EXTRACT_SUBREG (inst i32:$src0, i32:$src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0)
820 (inst $src0, $src1, $src2, 0 /* clamp */)
838 let HasClamp = 0;
839 let HasExtVOP3DPP = 0;
840 let HasExtDPP = 0;
847 let HasClamp = 0;
848 let HasExtVOP3DPP = 0;
849 let HasExtDPP = 0;
862 unsigned New = 0;
863 if (}] # modifier_idx # [{ == 0) {
864 New = (}] # dest_sel # [{ == 1) ? ((Val & 0x2) ? (SISrcMods::OP_SEL_0 | SISrcMods::DST_OP_SEL) : SISrcMods::DST_OP_SEL)
865 : ((Val & 0x2) ? SISrcMods::OP_SEL_0 : SISrcMods::NONE);
867 New = (Val & 0x1) ? SISrcMods::OP_SEL_0 : SISrcMods::NONE;
872 def SrcAndDstSelToOpSelXForm_0_0 : SrcAndDstSelToOpSelXForm<0,0>;
873 def SrcAndDstSelToOpSelXForm_0_1 : SrcAndDstSelToOpSelXForm<0,1>;
874 def SrcAndDstSelToOpSelXForm_1_0 : SrcAndDstSelToOpSelXForm<1,0>;
876 def SrcAndDstSelToOpSelXForm_2_0 : SrcAndDstSelToOpSelXForm<2,0>;
911 (V & 0x2) ? SISrcMods::DST_OP_SEL : SISrcMods::NONE,
922 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in)
934 let HasClamp = 0;
935 let HasOMod = 0;
936 let HasModifiers = 0;
939 0 /* HasIntClamp */, HasModifiers, HasSrc2Mods,
943 let InsVOP3OpSel = !con(getInsVOP3Base<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, 0, 1, 1, 0,
944 Src0Mod, Src1Mod, Src2Mod, 0>.ret,
948 let AsmVOP3OpSel = !subst("$op_sel", "$bitop3$op_sel", getAsmVOP3OpSel<3, 0, 0, 0, 0, 0>.ret);
956 let HasClamp = 0;
957 let HasSrc2 = 0;
958 let HasSrc2Mods = 0;
959 let HasExtVOP3DPP = 0;
961 let HasOMod = 0;
968 let HasClamp = 0;
969 let HasSrc2 = 0;
970 let HasSrc2Mods = 0;
971 let HasExtVOP3DPP = 0;
973 let HasOMod = 0;
981 let HasClamp = 0;
982 let HasExtVOP3DPP = 0;
984 let HasOMod = 0;
1005 let HasClamp = 0;
1006 let HasSrc2 = 0;
1013 let HasExtVOP3DPP = 0;
1023 let HasClamp = 0;
1024 let HasExtVOP3DPP = 0;
1026 let HasOMod = 0;
1035 let HasClamp = 0;
1036 let HasExtVOP3DPP = 0;
1038 let HasOMod = 0;
1047 let HasClamp = 0;
1048 let HasSrc2 = 0;
1049 let HasSrc2Mods = 0;
1050 let HasExtVOP3DPP = 0;
1052 let HasOMod = 0;
1059 let HasClamp = 0;
1060 let HasSrc2 = 0;
1061 let HasSrc2Mods = 0;
1062 let HasExtVOP3DPP = 0;
1064 let HasOMod = 0;
1068 let HasModifiers = 0;
1069 let HasSrc0IntMods = 0;
1070 let HasSrc1IntMods = 0;
1071 let HasOMod = 0;
1072 let HasOpSel = 0;
1073 let HasClamp = 0;
1074 let HasExtDPP = 0;
1075 let HasExt32BitDPP = 0;
1076 let HasExtVOP3DPP = 0;
1077 let HasExt64BitDPP = 0;
1080 let SubtargetPredicate = HasFP8ConversionScaleInsts, mayRaiseFPException = 0 in {
1096 let SubtargetPredicate = HasBF8ConversionScaleInsts, mayRaiseFPException = 0 in {
1112 let SubtargetPredicate = HasFP4ConversionScaleInsts, mayRaiseFPException = 0 in {
1133 let SubtargetPredicate = HasFP6BF6ConversionScaleInsts, mayRaiseFPException = 0, Constraints = "@earlyclobber $vdst" in {
1142 let SubtargetPredicate = HasF16BF16ToFP6BF6ConversionScaleInsts, mayRaiseFPException = 0, Constraints = "@earlyclobber $vdst" in {
1155 let SubtargetPredicate = HasGFX950Insts, mayRaiseFPException = 0 in {
1161 let ReadsModeReg = 0 in {
1166 (V_CVT_PK_F16_F32_e64 0, (EXTRACT_SUBREG VReg_64:$src, sub0), 0, (EXTRACT_SUBREG VReg_64:$src, sub1))>;
1168 (V_CVT_PK_F16_F32_e64 0, (V_CVT_F32_F64_e64 0, (EXTRACT_SUBREG VReg_128:$src, sub0_sub1)),
1169 0, (V_CVT_F32_F64_e64 0, (EXTRACT_SUBREG VReg_128:$src, sub2_sub3)))>;
1186 (inst !if(!eq(dst_sel, 0), (SrcAndDstSelToOpSelXForm_0_0 $src_sel), (SrcAndDstSelToOpSelXForm_0_1 $src_sel)), $src0,
1187 !if(!eq(dst_sel, 0), (SrcAndDstSelToOpSelXForm_1_0 $src_sel), (SrcAndDstSelToOpSelXForm_1_1 $src_sel)), $src1, VGPR_32:$vdst_in)
1189 foreach DstSel = [0, -1] in {
1196 (inst (DstSelToOpSelXForm $word_sel), $src0, 0, $src1, 0, $src2, VGPR_32:$vdst_in)
1203 (inst (SrcSelToOpSelXForm $word_sel), $src0, 0, $src1)
1214 (inst (DstSelToOpSelXForm $word_sel), $src0, 0, $src1, VGPR_32:$vdst_in)
1223 (inst (DstSelToOpSel3XForm $index), $src0, 0, $src1, (SrcAndDstSelToOpSelXForm_2_0 $index), $src2, VGPR_32:$vdst_in)
1230 (inst (DstSelToOpSel3XForm $index), $src0, 0, $src1, (SrcAndDstSelToOpSelXForm_2_0 $index), $src2)
1237 (inst (DstSelToOpSel3XForm $index), $src0, 0, $src1, (SrcAndDstSelToOpSelXForm_2_0 $index), $src2, VGPR_32:$vdst_in)
1278 (V_SUB_NC_U16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0)
1287 (V_SUB_NC_U16_t16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0)
1296 (V_SUB_NC_U16_fake16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0)
1325 (i16 (V_BITOP3_B16_e64 0, VSrc_b16:$src0, 0, VSrc_b16:$src1, 0, VSrc_b16:$src2, timm:$bitop3, 0))
1335 (i16 (V_BITOP3_B16_e64 0, VSrc_b16:$src0, 0, VSrc_b16:$src1, 0, VSrc_b16:$src2, timm:$bitop3, 0))
1358 let HasClamp = 0;
1359 let HasOMod = 0;
1363 let HasClamp = 0;
1364 let HasOMod = 0;
1371 let Src2ModVOP3DPP = FPT16VCSrcInputMods</*IsFake16*/0>;
1375 let HasClamp = 0;
1376 let HasOMod = 0;
1412 let ReadsModeReg = 0 in {
1416 (V_CVT_PK_BF16_F32_e64 0, (EXTRACT_SUBREG VReg_64:$src, sub0), 0, (EXTRACT_SUBREG VReg_64:$src, sub1))>;
1418 (V_CVT_PK_BF16_F32_e64 0, (V_CVT_F32_F64_e64 0, (EXTRACT_SUBREG VReg_128:$src, sub0_sub1)),
1419 0, (V_CVT_F32_F64_e64 0, (EXTRACT_SUBREG VReg_128:$src, sub2_sub3)))>;
1424 (V_CVT_PK_BF16_F32_e64 $src0_modifiers, $src0, 0, (f32 (IMPLICIT_DEF)))>;
1426 (V_CVT_PK_BF16_F32_e64 0, (f32 (V_CVT_F32_F64_e64 $src0_modifiers, $src0)), 0, (f32 (IMPLICIT_DEF)))>;
1431 (inst (DstSelToOpSelXForm $word_sel), $src0, 0, $src1, VGPR_32:$vdst_in)
1443 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
1448 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
1512 (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 )
1518 (inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 )
1523 def : AshrPkU8Pat<V_ASHR_PK_U8_I32_e64, 0, 255>;
1540 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
1541 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
1542 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
1591 defm V_MIN3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x229, "V_MIN3_F32", "v_min3_num_f32">;
1592 defm V_MAX3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x22a, "V_MAX3_F32", "v_max3_num_f32">;
1593 defm V_MIN3_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x22b, "v_min3_num_f16", "V_MIN3_F16", "v_min3_f16">;
1594 defm V_MAX3_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x22c, "v_max3_num_f16", "V_MAX3_F16", "v_max3_f16">;
1595 defm V_MINIMUM3_F32 : VOP3Only_Realtriple_gfx12<0x22d>;
1596 defm V_MAXIMUM3_F32 : VOP3Only_Realtriple_gfx12<0x22e>;
1597 defm V_MINIMUM3_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x22f, "v_minimum3_f16">;
1598 defm V_MAXIMUM3_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x230, "v_maximum3_f16">;
1599 defm V_MED3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x231, "V_MED3_F32", "v_med3_num_f32">;
1600 defm V_MED3_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x232, "v_med3_num_f16", "V_MED3_F16", "v_med3_f16">;
1601 defm V_MINMAX_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x268, "V_MINMAX_F32", "v_minmax_num_f32">;
1602 defm V_MAXMIN_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x269, "V_MAXMIN_F32", "v_maxmin_num_f32">;
1603 defm V_MINMAX_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x26a, "v_minmax_num_f16", "V_MINMAX_F16", "v_minmax_f16">;
1604 defm V_MAXMIN_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x26b, "v_maxmin_num_f16", "V_MAXMIN_F16", "v_maxmin_f16">;
1605 defm V_MINIMUMMAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x26c>;
1606 defm V_MAXIMUMMINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x26d>;
1607 defm V_MINIMUMMAXIMUM_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x26e, "v_minimummaximum_f16">;
1608 defm V_MAXIMUMMINIMUM_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x26f, "v_maximumminimum_f16">;
1609 defm V_S_EXP_F32 : VOP3Only_Real_Base_gfx12<0x280>;
1610 defm V_S_EXP_F16 : VOP3Only_Real_Base_gfx12<0x281>;
1611 defm V_S_LOG_F32 : VOP3Only_Real_Base_gfx12<0x282>;
1612 defm V_S_LOG_F16 : VOP3Only_Real_Base_gfx12<0x283>;
1613 defm V_S_RCP_F32 : VOP3Only_Real_Base_gfx12<0x284>;
1614 defm V_S_RCP_F16 : VOP3Only_Real_Base_gfx12<0x285>;
1615 defm V_S_RSQ_F32 : VOP3Only_Real_Base_gfx12<0x286>;
1616 defm V_S_RSQ_F16 : VOP3Only_Real_Base_gfx12<0x287>;
1617 defm V_S_SQRT_F32 : VOP3Only_Real_Base_gfx12<0x288>;
1618 defm V_S_SQRT_F16 : VOP3Only_Real_Base_gfx12<0x289>;
1619 defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12<0x2fe, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
1620 defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12<0x2ff, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
1621 defm V_MINIMUM_F64 : VOP3Only_Real_Base_gfx12<0x341>;
1622 defm V_MAXIMUM_F64 : VOP3Only_Real_Base_gfx12<0x342>;
1623 defm V_MINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x365>;
1624 defm V_MAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x366>;
1625 defm V_MINIMUM_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x367, "v_minimum_f16">;
1626 defm V_MAXIMUM_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx12<0x368, "v_maximum_f16">;
1628 defm V_PERMLANE16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x30f>;
1629 defm V_PERMLANEX16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x310>;
1631 defm V_CVT_PK_FP8_F32 : VOP3Only_Realtriple_gfx12<0x369>;
1632 defm V_CVT_PK_BF8_F32 : VOP3Only_Realtriple_gfx12<0x36a>;
1633 defm V_CVT_SR_FP8_F32_gfx12 : VOP3_Realtriple_with_name_gfx12<0x36b, "V_CVT_SR_FP8_F32_gfx12", "v_cvt_sr_fp8_f32" >;
1634 defm V_CVT_SR_BF8_F32_gfx12 : VOP3_Realtriple_with_name_gfx12<0x36c, "V_CVT_SR_BF8_F32_gfx12", "v_cvt_sr_bf8_f32">;
1657 defm _t16: VOP3Dot_Realtriple_gfx11_gfx12<op, asmName, 0, opName#"_t16">;
1658 defm _fake16: VOP3Dot_Realtriple_gfx11_gfx12<op, asmName, 0, opName#"_fake16">;
1662 string pseudo_mnemonic = "", bit isSingle = 0> :
1667 string pseudo_mnemonic = "", bit isSingle = 0> {
1679 defm V_FMA_DX9_ZERO_F32 : VOP3_Real_with_name_gfx11_gfx12<0x209, "V_FMA_LEGACY_F32", "v_fma_dx9_zero_f32">;
1680 defm V_MAD_I32_I24 : VOP3_Realtriple_gfx11_gfx12<0x20a>;
1681 defm V_MAD_U32_U24 : VOP3_Realtriple_gfx11_gfx12<0x20b>;
1682 defm V_CUBEID_F32 : VOP3_Realtriple_gfx11_gfx12<0x20c>;
1683 defm V_CUBESC_F32 : VOP3_Realtriple_gfx11_gfx12<0x20d>;
1684 defm V_CUBETC_F32 : VOP3_Realtriple_gfx11_gfx12<0x20e>;
1685 defm V_CUBEMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x20f>;
1686 defm V_BFE_U32 : VOP3_Realtriple_gfx11_gfx12<0x210>;
1687 defm V_BFE_I32 : VOP3_Realtriple_gfx11_gfx12<0x211>;
1688 defm V_BFI_B32 : VOP3_Realtriple_gfx11_gfx12<0x212>;
1689 defm V_FMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x213>;
1690 defm V_FMA_F64 : VOP3_Real_Base_gfx11_gfx12<0x214>;
1691 defm V_LERP_U8 : VOP3_Realtriple_gfx11_gfx12<0x215>;
1692 defm V_ALIGNBIT_B32 : VOP3_Realtriple_gfx11_gfx12<0x216>;
1693 defm V_ALIGNBYTE_B32 : VOP3_Realtriple_gfx11_gfx12<0x217>;
1694 defm V_MULLIT_F32 : VOP3_Realtriple_gfx11_gfx12<0x218>;
1695 defm V_MIN3_F32 : VOP3_Realtriple_gfx11<0x219>;
1696 defm V_MIN3_I32 : VOP3_Realtriple_gfx11_gfx12<0x21a>;
1697 defm V_MIN3_U32 : VOP3_Realtriple_gfx11_gfx12<0x21b>;
1698 defm V_MAX3_F32 : VOP3_Realtriple_gfx11<0x21c>;
1699 defm V_MAX3_I32 : VOP3_Realtriple_gfx11_gfx12<0x21d>;
1700 defm V_MAX3_U32 : VOP3_Realtriple_gfx11_gfx12<0x21e>;
1701 defm V_MED3_F32 : VOP3_Realtriple_gfx11<0x21f>;
1702 defm V_MED3_I32 : VOP3_Realtriple_gfx11_gfx12<0x220>;
1703 defm V_MED3_U32 : VOP3_Realtriple_gfx11_gfx12<0x221>;
1704 defm V_SAD_U8 : VOP3_Realtriple_gfx11_gfx12<0x222>;
1705 defm V_SAD_HI_U8 : VOP3_Realtriple_gfx11_gfx12<0x223>;
1706 defm V_SAD_U16 : VOP3_Realtriple_gfx11_gfx12<0x224>;
1707 defm V_SAD_U32 : VOP3_Realtriple_gfx11_gfx12<0x225>;
1708 defm V_CVT_PK_U8_F32 : VOP3_Realtriple_gfx11_gfx12<0x226>;
1709 defm V_DIV_FIXUP_F32 : VOP3_Real_Base_gfx11_gfx12<0x227>;
1710 defm V_DIV_FIXUP_F64 : VOP3_Real_Base_gfx11_gfx12<0x228>;
1711 defm V_DIV_FMAS_F32 : VOP3_Real_Base_gfx11_gfx12<0x237>;
1712 defm V_DIV_FMAS_F64 : VOP3_Real_Base_gfx11_gfx12<0x238>;
1713 defm V_MSAD_U8 : VOP3_Realtriple_gfx11_gfx12<0x239>;
1714 defm V_QSAD_PK_U16_U8 : VOP3_Real_Base_gfx11_gfx12<0x23a>;
1715 defm V_MQSAD_PK_U16_U8 : VOP3_Real_Base_gfx11_gfx12<0x23b>;
1716 defm V_MQSAD_U32_U8 : VOP3_Real_Base_gfx11_gfx12<0x23d>;
1717 defm V_XOR3_B32 : VOP3_Realtriple_gfx11_gfx12<0x240>;
1718 defm V_MAD_U16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x241, "v_mad_u16", "V_MAD_U16_gfx9">;
1719 defm V_PERM_B32 : VOP3_Realtriple_gfx11_gfx12<0x244>;
1720 defm V_XAD_U32 : VOP3_Realtriple_gfx11_gfx12<0x245>;
1721 defm V_LSHL_ADD_U32 : VOP3_Realtriple_gfx11_gfx12<0x246>;
1722 defm V_ADD_LSHL_U32 : VOP3_Realtriple_gfx11_gfx12<0x247>;
1723 defm V_FMA_F16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x248, "v_fma_f16", "V_FMA_F16_gfx9">;
1724 defm V_MIN3_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx11<0x249, "v_min3_f16">;
1725 defm V_MIN3_I16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x24a, "v_min3_i16">;
1726 defm V_MIN3_U16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x24b, "v_min3_u16">;
1727 defm V_MAX3_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx11<0x24c, "v_max3_f16">;
1728 defm V_MAX3_I16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x24d, "v_max3_i16">;
1729 defm V_MAX3_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x24e, "v_max3_u16">;
1730 defm V_MED3_F16 : VOP3Only_Realtriple_t16_and_fake16_gfx11<0x24f, "v_med3_f16">;
1731 defm V_MED3_I16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x250, "v_med3_i16">;
1732 defm V_MED3_U16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x251, "v_med3_u16">;
1733 defm V_MAD_I16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x253, "v_mad_i16", "V_MAD_I16_gfx9">;
1734 defm V_DIV_FIXUP_F16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x254, "v_div_fixup_f16", "V_DIV_FIXUP_F16_gfx9">;
1735 defm V_ADD3_U32 : VOP3_Realtriple_gfx11_gfx12<0x255>;
1736 defm V_LSHL_OR_B32 : VOP3_Realtriple_gfx11_gfx12<0x256>;
1737 defm V_AND_OR_B32 : VOP3_Realtriple_gfx11_gfx12<0x257>;
1738 defm V_OR3_B32 : VOP3_Realtriple_gfx11_gfx12<0x258>;
1739 defm V_MAD_U32_U16 : VOP3_Realtriple_gfx11_gfx12<0x259>;
1740 defm V_MAD_I32_I16 : VOP3_Realtriple_gfx11_gfx12<0x25a>;
1741 defm V_PERMLANE16_B32 : VOP3_Real_Base_gfx11_gfx12<0x25b>;
1742 defm V_PERMLANEX16_B32 : VOP3_Real_Base_gfx11_gfx12<0x25c>;
1743 defm V_MAXMIN_F32 : VOP3_Realtriple_gfx11<0x25e>;
1744 defm V_MINMAX_F32 : VOP3_Realtriple_gfx11<0x25f>;
1745 defm V_MAXMIN_F16 : VOP3_Realtriple_t16_and_fake16_gfx11<0x260, "v_maxmin_f16">;
1746 defm V_MINMAX_F16 : VOP3_Realtriple_t16_and_fake16_gfx11<0x261, "v_minmax_f16">;
1747 defm V_MAXMIN_U32 : VOP3_Realtriple_gfx11_gfx12<0x262>;
1748 defm V_MINMAX_U32 : VOP3_Realtriple_gfx11_gfx12<0x263>;
1749 defm V_MAXMIN_I32 : VOP3_Realtriple_gfx11_gfx12<0x264>;
1750 defm V_MINMAX_I32 : VOP3_Realtriple_gfx11_gfx12<0x265>;
1751 defm V_DOT2_F16_F16 : VOP3Dot_Realtriple_t16_and_fake16_gfx11_gfx12<0x266, "v_dot2_f16_f16">;
1752 defm V_DOT2_BF16_BF16 : VOP3Dot_Realtriple_t16_and_fake16_gfx11_gfx12<0x267, "v_dot2_bf16_bf16">;
1753 defm V_DIV_SCALE_F32 : VOP3be_Real_gfx11_gfx12<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">;
1754 defm V_DIV_SCALE_F64 : VOP3be_Real_gfx11_gfx12<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">;
1755 defm V_MAD_U64_U32_gfx11 : VOP3be_Real_gfx11<0x2fe, "V_MAD_U64_U32_gfx11", "v_mad_u64_u32">;
1756 defm V_MAD_I64_I32_gfx11 : VOP3be_Real_gfx11<0x2ff, "V_MAD_I64_I32_gfx11", "v_mad_i64_i32">;
1757 defm V_ADD_NC_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x303, "v_add_nc_u16">;
1758 defm V_SUB_NC_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x304, "v_sub_nc_u16">;
1759 defm V_MUL_LO_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x305, "v_mul_lo_u16">;
1760 defm V_CVT_PK_I16_F32 : VOP3_Realtriple_gfx11_gfx12<0x306>;
1761 defm V_CVT_PK_U16_F32 : VOP3_Realtriple_gfx11_gfx12<0x307>;
1762 defm V_MAX_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x309, "v_max_u16">;
1763 defm V_MAX_I16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x30a, "v_max_i16">;
1764 defm V_MIN_U16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x30b, "v_min_u16">;
1765 defm V_MIN_I16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x30c, "v_min_i16">;
1766 defm V_ADD_NC_I16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x30d, "v_add_nc_i16", "V_ADD_I16">;
1767 defm V_SUB_NC_I16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x30e, "v_sub_nc_i16", "V_SUB_I16">;
1768 defm V_PACK_B32_F16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x311, "v_pack_b32_f16">;
1769 defm V_CVT_PK_NORM_I16_F16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x312, "v_cvt_pk_norm_i16_f16", "V_CVT_PKNORM_I16_F16", "v_cvt_pknorm_i16_f16">;
1770 defm V_CVT_PK_NORM_U16_F16 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x313, "v_cvt_pk_norm_u16_f16", "V_CVT_PKNORM_U16_F16", "v_cvt_pknorm_u16_f16">;
1771 defm V_SUB_NC_I32 : VOP3_Realtriple_with_name_gfx11_gfx12<0x325, "V_SUB_I32", "v_sub_nc_i32">;
1772 defm V_ADD_NC_I32 : VOP3_Realtriple_with_name_gfx11_gfx12<0x326, "V_ADD_I32", "v_add_nc_i32">;
1773 defm V_ADD_F64 : VOP3_Real_Base_gfx11<0x327>;
1774 defm V_MUL_F64 : VOP3_Real_Base_gfx11<0x328>;
1775 defm V_MIN_F64 : VOP3_Real_Base_gfx11<0x329>;
1776 defm V_MAX_F64 : VOP3_Real_Base_gfx11<0x32a>;
1777 defm V_LDEXP_F64 : VOP3_Real_Base_gfx11_gfx12<0x32b>;
1778 defm V_MUL_LO_U32 : VOP3_Real_Base_gfx11_gfx12<0x32c>;
1779 defm V_MUL_HI_U32 : VOP3_Real_Base_gfx11_gfx12<0x32d>;
1780 defm V_MUL_HI_I32 : VOP3_Real_Base_gfx11_gfx12<0x32e>;
1781 defm V_TRIG_PREOP_F64 : VOP3_Real_Base_gfx11_gfx12<0x32f>;
1782 defm V_LSHLREV_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x338, "v_lshlrev_b16">;
1783 defm V_LSHRREV_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x339, "v_lshrrev_b16">;
1784 defm V_ASHRREV_I16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x33a, "v_ashrrev_i16">;
1785 defm V_LSHLREV_B64 : VOP3_Real_Base_gfx11<0x33c>;
1786 defm V_LSHRREV_B64 : VOP3_Real_Base_gfx11_gfx12<0x33d>;
1787 defm V_ASHRREV_I64 : VOP3_Real_Base_gfx11_gfx12<0x33e>;
1788 defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11_gfx12<0x360>; // Pseudo in VOP2
1790 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11_gfx12<0x361>; // Pseudo in VOP2
1792 defm V_AND_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x362, "v_and_b16">;
1793 defm V_OR_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x363, "v_or_b16">;
1794 defm V_XOR_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x364, "v_xor_b16">;
1852 defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>;
1855 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>;
1859 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>;
1862 defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>;
1863 defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>;
1864 defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>;
1865 defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>;
1866 defm V_PERM_B32 : VOP3_Real_gfx10<0x344>;
1867 defm V_XAD_U32 : VOP3_Real_gfx10<0x345>;
1868 defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>;
1869 defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>;
1870 defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>;
1871 defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>;
1872 defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>;
1873 defm V_OR3_B32 : VOP3_Real_gfx10<0x372>;
1877 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">;
1879 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">;
1881 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">;
1883 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">;
1885 defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>;
1886 defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>;
1887 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>;
1889 defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>;
1890 defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>;
1891 defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>;
1893 defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>;
1894 defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>;
1895 defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>;
1897 defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>;
1898 defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>;
1899 defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>;
1900 defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>;
1901 defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>;
1902 defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>;
1903 defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>;
1904 defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>;
1905 defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>;
1906 defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>;
1907 defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>;
1910 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">;
1912 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">;
1914 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">;
1916 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
1918 defm V_ADD_NC_U16 : VOP3OpSel_Real_gfx10<0x303>;
1919 defm V_SUB_NC_U16 : VOP3OpSel_Real_gfx10<0x304>;
1923 defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">;
1924 defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">;
1925 defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">;
1926 defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">;
1927 defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">;
1928 defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">;
1929 defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">;
1930 defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">;
1931 defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>;
1932 defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>;
1942 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1947 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1957 defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>;
1958 defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>;
1959 defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>;
1960 defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>;
1970 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1975 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1985 defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>;
1986 defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>;
1987 defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>;
1988 defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>;
1990 defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
1991 defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
1992 defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>;
1993 defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>;
1994 defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>;
1995 defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>;
1996 defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>;
1997 defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>;
1998 defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>;
1999 defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>;
2000 defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>;
2001 defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>;
2002 defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>;
2003 defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>;
2004 defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>;
2005 defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>;
2006 defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>;
2007 defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>;
2008 defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>;
2009 defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>;
2010 defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>;
2011 defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>;
2012 defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>;
2013 defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>;
2014 defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>;
2015 defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>;
2016 defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>;
2017 defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>;
2018 defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>;
2019 defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>;
2020 defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>;
2021 defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>;
2022 defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>;
2023 defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>;
2024 defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>;
2025 defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>;
2026 defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>;
2027 defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
2028 defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
2029 defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
2030 defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
2031 defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
2032 defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
2033 defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>;
2034 defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>;
2035 defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>;
2036 defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>;
2037 defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>;
2041 defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>;
2130 multiclass VOP3_Real_BITOP3_gfx9<bits<10> op, string AsmName, bit isSingle = 0> {
2139 let Inst{63-61} = bitop3{2-0};
2140 let Inst{11} = !if(ps.Pfl.HasOpSel, src0_modifiers{2}, 0);
2141 let Inst{12} = !if(ps.Pfl.HasOpSel, src1_modifiers{2}, 0);
2142 let Inst{13} = !if(ps.Pfl.HasOpSel, src2_modifiers{2}, 0);
2143 let Inst{14} = !if(ps.Pfl.HasOpSel, src0_modifiers{3}, 0);
2150 defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
2151 defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;
2153 defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
2154 defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
2155 defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
2156 defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
2157 defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
2158 defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
2159 defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
2160 defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
2161 defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
2162 defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
2163 defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
2164 defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
2165 defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
2166 defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
2167 defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
2168 defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
2169 defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
2170 defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
2171 defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
2172 defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
2173 defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
2174 defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
2175 defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
2176 defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
2177 defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
2178 defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
2179 defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
2180 defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
2181 defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
2182 defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
2183 defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
2184 defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
2185 defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
2186 defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
2187 defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
2188 defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
2189 defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
2190 defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
2191 defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
2192 defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
2194 defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
2196 defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>;
2197 defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>;
2198 defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
2199 defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
2200 defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
2201 defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>;
2204 defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
2205 defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
2206 defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
2207 defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
2210 defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
2211 defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
2213 defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
2214 defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
2215 defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
2216 defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
2217 defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
2218 defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
2220 defm V_ADD_I32 : VOP3_Real_vi <0x29c>;
2221 defm V_SUB_I32 : VOP3_Real_vi <0x29d>;
2223 defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
2224 defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
2225 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
2227 defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
2228 defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
2229 defm V_ADD_F64 : VOP3_Real_vi <0x280>;
2230 defm V_MUL_F64 : VOP3_Real_vi <0x281>;
2231 defm V_MIN_F64 : VOP3_Real_vi <0x282>;
2232 defm V_MAX_F64 : VOP3_Real_vi <0x283>;
2233 defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
2234 defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
2238 defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
2241 defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
2242 defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
2244 defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>;
2245 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>;
2247 defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
2248 defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
2249 defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
2250 defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;
2252 defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
2253 defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
2254 defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
2255 defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
2256 defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
2257 defm V_OR3_B32 : VOP3_Real_vi <0x202>;
2258 defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
2260 defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
2262 defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
2263 defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
2264 defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
2266 defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
2267 defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
2268 defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
2270 defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
2271 defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
2272 defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
2274 defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>;
2275 defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>;
2277 defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
2278 defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
2280 defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
2281 defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
2283 defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>;
2285 defm V_CVT_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x2a2>;
2286 defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>;
2287 defm V_CVT_PK_BF16_F32: VOP3OpSel_Real_gfx9 <0x268>;
2288 defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>;
2289 defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>;
2291 defm V_MINIMUM3_F32 : VOP3_Real_vi <0x2a8>;
2292 defm V_MAXIMUM3_F32 : VOP3_Real_vi <0x2a9>;
2294 defm V_BITOP3_B16 : VOP3_Real_BITOP3_gfx9<0x233, "v_bitop3_b16">;
2295 defm V_BITOP3_B32 : VOP3_Real_BITOP3_gfx9<0x234, "v_bitop3_b32">;
2297 defm V_CVT_SCALEF32_SR_FP8_BF16 : VOP3OpSel_Real_gfx9<0x246>;
2298 defm V_CVT_SCALEF32_SR_FP8_F16 : VOP3OpSel_Real_gfx9<0x242>;
2299 defm V_CVT_SCALEF32_SR_FP8_F32 : VOP3OpSel_Real_gfx9<0x237>;
2300 defm V_CVT_SCALEF32_F16_FP8 : VOP3OpSel_Real_gfx9 <0x24a>;
2301 defm V_CVT_SCALEF32_F32_FP8 : VOP3OpSel_Real_gfx9 <0x23b>;
2302 defm V_CVT_SCALEF32_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x235>;
2303 defm V_CVT_SCALEF32_PK_F32_FP8 : VOP3OpSel_Real_gfx9 <0x239>;
2304 defm V_CVT_SCALEF32_PK_FP8_F16 : VOP3OpSel_Real_gfx9 <0x240>;
2305 defm V_CVT_SCALEF32_PK_FP8_BF16: VOP3OpSel_Real_gfx9 <0x244>;
2306 defm V_CVT_SCALEF32_PK_F16_FP8 : VOP3OpSel_Real_gfx9<0x248>;
2307 defm V_CVT_SCALEF32_PK_BF16_FP8 : VOP3OpSel_Real_gfx9<0x269>;
2310 defm V_CVT_SCALEF32_SR_BF8_BF16 : VOP3OpSel_Real_gfx9<0x247>;
2311 defm V_CVT_SCALEF32_SR_BF8_F16 : VOP3OpSel_Real_gfx9<0x243>;
2312 defm V_CVT_SCALEF32_SR_BF8_F32 : VOP3OpSel_Real_gfx9<0x238>;
2313 defm V_CVT_SCALEF32_F16_BF8 : VOP3OpSel_Real_gfx9 <0x24b>;
2314 defm V_CVT_SCALEF32_F32_BF8 : VOP3OpSel_Real_gfx9 <0x23c>;
2315 defm V_CVT_SCALEF32_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x236>;
2316 defm V_CVT_SCALEF32_PK_F32_BF8 : VOP3OpSel_Real_gfx9 <0x23a>;
2317 defm V_CVT_SCALEF32_PK_BF8_F16 : VOP3OpSel_Real_gfx9 <0x241>;
2318 defm V_CVT_SCALEF32_PK_BF8_BF16: VOP3OpSel_Real_gfx9 <0x245>;
2319 defm V_CVT_SCALEF32_PK_F16_BF8 : VOP3OpSel_Real_gfx9<0x249>;
2320 defm V_CVT_SCALEF32_PK_BF16_BF8 : VOP3OpSel_Real_gfx9<0x26a>;
2323 defm V_CVT_SCALEF32_PK_F32_FP4 : VOP3OpSel_Real_gfx9 <0x23f>;
2324 defm V_CVT_SCALEF32_PK_FP4_F32 : VOP3OpSel_Real_gfx9 <0x23d>;
2325 defm V_CVT_SCALEF32_PK_F16_FP4 : VOP3OpSel_Real_gfx9 <0x250>;
2326 defm V_CVT_SCALEF32_PK_BF16_FP4 : VOP3OpSel_Real_gfx9 <0x251>;
2327 defm V_CVT_SCALEF32_PK_FP4_F16 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x24c>;
2328 defm V_CVT_SCALEF32_PK_FP4_BF16: VOP3OpSel_Real_gfx9_forced_opsel2 <0x24d>;
2329 defm V_CVT_SCALEF32_SR_PK_FP4_F16: VOP3OpSel_Real_gfx9 <0x24e>;
2330 defm V_CVT_SCALEF32_SR_PK_FP4_BF16: VOP3OpSel_Real_gfx9 <0x24f>;
2331 defm V_CVT_SCALEF32_SR_PK_FP4_F32: VOP3OpSel_Real_gfx9 <0x23e>;
2334 defm V_CVT_SCALEF32_PK32_F32_FP6 : VOP3_Real_gfx9<0x256, "v_cvt_scalef32_pk32_f32_fp6">;
2335 defm V_CVT_SCALEF32_PK32_F32_BF6 : VOP3_Real_gfx9<0x257, "v_cvt_scalef32_pk32_f32_bf6">;
2336 defm V_CVT_SCALEF32_PK32_F16_FP6 : VOP3_Real_gfx9<0x260, "v_cvt_scalef32_pk32_f16_fp6">;
2337 defm V_CVT_SCALEF32_PK32_BF16_FP6 : VOP3_Real_gfx9<0x261, "v_cvt_scalef32_pk32_bf16_fp6">;
2338 defm V_CVT_SCALEF32_PK32_F16_BF6 : VOP3_Real_gfx9<0x262, "v_cvt_scalef32_pk32_f16_bf6">;
2339 defm V_CVT_SCALEF32_PK32_BF16_BF6 : VOP3_Real_gfx9<0x263, "v_cvt_scalef32_pk32_bf16_bf6">;
2343 defm V_CVT_SCALEF32_PK32_FP6_F16 : VOP3_Real_gfx9<0x258, "v_cvt_scalef32_pk32_fp6_f16">;
2344 defm V_CVT_SCALEF32_PK32_FP6_BF16 : VOP3_Real_gfx9<0x259, "v_cvt_scalef32_pk32_fp6_bf16">;
2345 defm V_CVT_SCALEF32_PK32_BF6_F16 : VOP3_Real_gfx9<0x25a, "v_cvt_scalef32_pk32_bf6_f16">;
2346 defm V_CVT_SCALEF32_PK32_BF6_BF16 : VOP3_Real_gfx9<0x25b, "v_cvt_scalef32_pk32_bf6_bf16">;
2347 defm V_CVT_SCALEF32_SR_PK32_BF6_BF16 : VOP3_Real_gfx9<0x25f, "v_cvt_scalef32_sr_pk32_bf6_bf16">;
2348 defm V_CVT_SCALEF32_SR_PK32_BF6_F16 : VOP3_Real_gfx9<0x25e, "v_cvt_scalef32_sr_pk32_bf6_f16">;
2349 defm V_CVT_SCALEF32_SR_PK32_BF6_F32 : VOP3_Real_gfx9<0x255, "v_cvt_scalef32_sr_pk32_bf6_f32">;
2350 defm V_CVT_SCALEF32_SR_PK32_FP6_BF16 : VOP3_Real_gfx9<0x25d, "v_cvt_scalef32_sr_pk32_fp6_bf16">;
2351 defm V_CVT_SCALEF32_SR_PK32_FP6_F16 : VOP3_Real_gfx9<0x25c, "v_cvt_scalef32_sr_pk32_fp6_f16">;
2352 defm V_CVT_SCALEF32_SR_PK32_FP6_F32 : VOP3_Real_gfx9<0x254, "v_cvt_scalef32_sr_pk32_fp6_f32">;
2356 defm V_CVT_SR_F16_F32 : VOP3OpSel_Real_gfx9 <0x2a6>;
2357 defm V_CVT_SR_BF16_F32: VOP3OpSel_Real_gfx9 <0x2a7>;
2360 defm V_ASHR_PK_I8_I32 : VOP3OpSel_Real_gfx9 <0x265>;
2361 defm V_ASHR_PK_U8_I32 : VOP3OpSel_Real_gfx9 <0x266>;
2363 defm V_CVT_PK_F16_F32 : VOP3_Real_gfx9<0x267, "v_cvt_pk_f16_f32">;
2366 defm V_CVT_SCALEF32_2XPK16_FP6_F32 : VOP3_Real_gfx9<0x252, "v_cvt_scalef32_2xpk16_fp6_f32">;
2367 defm V_CVT_SCALEF32_2XPK16_BF6_F32 : VOP3_Real_gfx9<0x253, "v_cvt_scalef32_2xpk16_bf6_f32">;