Lines Matching +full:0 +full:x301
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
19 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
20 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
22 let Inst{31} = 0x0; //encoding
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
32 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
33 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
35 let Inst{31} = 0x0; // encoding
43 let Inst{8-0} = 0xf9; // sdwa
44 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
45 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
47 let Inst{31} = 0x0; // encoding
54 let Inst{8-0} = 0xf9; // sdwa
55 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
56 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
58 let Inst{31} = 0x0; // encoding
59 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
68 let mayLoad = 0;
69 let mayStore = 0;
70 let hasSideEffects = 0;
90 let isPseudo = 0;
91 let isCodeGenOnly = 0;
323 : VOP2eInst_Base<opName, P, 0, "", node, revOp, useSGPRInput>;
372 field bit HasExt = 0;
380 let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;
403 field bit HasExt = 0;
411 let DstRC = getVALUDstForVT<DstVT, 1/*IsTrue16*/, 0/*IsVOP3Encoding*/>.ret;
428 0, HasModifiers, HasModifiers, HasOMod,
437 0, HasModifiers, HasModifiers, HasOMod,
462 let AsmDPP8 = getAsmDPP8<1, 2, 0, vt0>.ret;
469 0 /*Src2HasMods*/, DstVT>.ret;
470 let HasSrc2 = 0;
471 let HasSrc2Mods = 0;
477 let HasExtSDWA9 = 0;
487 let Src0RC32 = getVOPSrc0ForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
488 let Src1RC32 = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
489 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret:$src2);
490 let Src0DPP = getVregSrcForVT<Src0VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
491 let Src1DPP = getVregSrcForVT<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
492 let Src2DPP = getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
493 let Src0ModDPP = getSrcModDPP_t16<Src0VT, 0/*IsFake16*/>.ret;
494 let Src1ModDPP = getSrcModDPP_t16<Src1VT, 0/*IsFake16*/>.ret;
495 let Src2ModDPP = getSrcModDPP_t16<Src2VT, 0/*IsFake16*/>.ret;
498 getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret:$src2, // stub argument
503 getVregSrcForVT<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret:$src2, // stub argument
509 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
510 let Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT, 0/*IsFake16*/>.ret;
511 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<Src0VT, DstVT, 0/*IsFake16*/>.ret;
512 let Src1ModVOP3DPP = getSrcModVOP3DPP<Src1VT, 0/*IsFake16*/>.ret;
513 let Src2ModVOP3DPP = getSrcModVOP3DPP<Src2VT, 0/*IsFake16*/>.ret;
514 let Src0Mod = getSrc0Mod<Src0VT, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
515 let Src1Mod = getSrcMod<Src1VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
516 let Src2Mod = getSrcMod<Src2VT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
552 let HasExtDPP = 0, HasExt32BitDPP = 0 in
554 let HasExtSDWA = 0, HasExt32BitDPP = 0, HasExt64BitDPP = 1 in
558 let HasClamp = 0;
559 let HasExtSDWA = 0;
560 let HasOpSel = 0;
561 let IsPacked = 0;
577 let HasExtVOP3DPP = 0;
619 let HasSrc2Mods = 0;
683 let HasSrc0IntMods = 0;
684 let HasSrc1IntMods = 0;
725 let Src0Mod = getSrc0Mod<f16, DstVT, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
726 let Src1Mod = getSrcMod<f16, 1/*IsTrue16*/, 0/*IsFake16*/>.ret;
727 let HasSrc2Mods = 0;
730 HasClamp, 1/*HasModifiers*/, 0/*HasSrc2Mods*/, HasOMod,
733 let Src1VOP3DPP = getVOP3DPPSrcForVT<Src1VT, 0/*IsFake16*/>.ret;
734 let Src0ModVOP3DPP = getSrc0ModVOP3DPP<f16, DstVT, 0/*IsFake16*/>.ret;
735 let Src1ModVOP3DPP = getSrcModVOP3DPP<f16, 0/*IsFake16*/>.ret;
758 let HasExt = 0;
759 let HasExtDPP = 0;
760 let HasExt32BitDPP = 0;
761 let HasExt64BitDPP = 0;
762 let HasExtSDWA = 0;
763 let HasExtSDWA9 = 0;
773 let HasSrc2 = 0;
774 let HasSrc2Mods = 0;
776 let HasExt = 0;
777 let HasExtDPP = 0;
778 let HasExt32BitDPP = 0;
779 let HasExt64BitDPP = 0;
780 let HasExtSDWA = 0;
781 let HasExtSDWA9 = 0;
792 defm V_CNDMASK_B32 : VOP2eInst_VOPD <"v_cndmask_b32", VOP2e_I32_I32_I32_I1, 0x9, "v_cndmask_b32">;
798 defm V_ADD_F32 : VOP2Inst_VOPD <"v_add_f32", VOP_F32_F32_F32, 0x4, "v_add_f32", any_fadd>;
799 defm V_SUB_F32 : VOP2Inst_VOPD <"v_sub_f32", VOP_F32_F32_F32, 0x5, "v_sub_f32", any_fsub>;
800 defm V_SUBREV_F32 : VOP2Inst_VOPD <"v_subrev_f32", VOP_F32_F32_F32, 0x6, "v_subrev_f32", null_frag, "v_sub_f32">;
801 defm V_MUL_LEGACY_F32 : VOP2Inst_VOPD <"v_mul_legacy_f32", VOP_F32_F32_F32, 0x7, "v_mul_dx9_zero_f32", AMDGPUfmul_legacy>;
802 defm V_MUL_F32 : VOP2Inst_VOPD <"v_mul_f32", VOP_F32_F32_F32, 0x3, "v_mul_f32", any_fmul>;
807 defm V_MIN_F32 : VOP2Inst_VOPD <"v_min_f32", VOP_F32_F32_F32, 0xb, "v_min_f32", fminnum_like>;
808 defm V_MAX_F32 : VOP2Inst_VOPD <"v_max_f32", VOP_F32_F32_F32, 0xa, "v_max_f32", fmaxnum_like>;
815 defm V_LSHLREV_B32 : VOP2Inst_VOPD <"v_lshlrev_b32", VOP_I32_I32_I32, 0x11, "v_lshlrev_b32", clshl_rev_32, "v_lshl_b32">;
816 defm V_AND_B32 : VOP2Inst_VOPD <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, 0x12, "v_and_b32", and>;
821 let mayRaiseFPException = 0 in {
835 } // End mayRaiseFPException = 0
851 defm V_ADD_U32 : VOP2Inst_VOPD <"v_add_u32", VOP_I32_I32_I32_ARITH, 0x10, "v_add_nc_u32", null_frag, "v_add_u32">;
888 let ReadsModeReg = 0, mayRaiseFPException = 0 in {
927 (Inst $src0, $src1, 0),
928 (Inst $src1, $src0, 0)
991 let HasSrc1FloatMods = 0;
995 let Src1Mod = IntT16InputMods<0/*IsFake16*/>;
996 let Src1ModDPP = IntT16_Lo128VRegInputMods<0/*IsFake16*/>;
997 let Src1ModVOP3DPP = IntT16VCSrcInputMods<0/*IsFake16*/>;
1053 0) /* op_sel */
1120 let mayRaiseFPException = 0 in {
1178 defm V_FMAC_F32 : VOP2Inst_VOPD <"v_fmac_f32", VOP_MAC_F32, 0x0, "v_fmac_f32">;
1205 defm V_DOT2C_F32_F16 : VOP2Inst_VOPD<"v_dot2c_f32_f16", VOP_DOT_ACC_F32_V2F16, 0xc, "v_dot2acc_f32_f16">;
1215 defm V_DOT2C_F32_BF16 : VOP2Inst_VOPD<"v_dot2c_f32_bf16", VOP_DOT_ACC_F32_V2BF16, 0xd, "v_dot2acc_f32_bf16">;
1252 def V_FMAMK_F32 : VOP2_Pseudo<"v_fmamk_f32", VOP_MADMK_F32, [], "">, VOPD_Component<0x2, "v_fmamk_f32">;
1255 def V_FMAAK_F32 : VOP2_Pseudo<"v_fmaak_f32", VOP_MADAK_F32, [], "">, VOPD_Component<0x1, "v_fmaak_f32">;
1262 // Note: 16-bit instructions produce a 0 result in the high 16-bits
1275 (V_MOV_B32_e32 (i32 0)), sub1)
1281 (V_CNDMASK_B32_e64 (i32 0/*src0mod*/), (i32 0/*src0*/),
1282 (i32 0/*src1mod*/), (i32 1/*src1*/),
1354 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
1355 /*src1mod*/(i32 0), /*src1*/(i32 -1), $src)
1399 bit IsDPP16 = 0> :
1408 let Inst{8-0} = 0xfa;
1409 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);
1410 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
1412 let Inst{31} = 0x0;
1448 let Inst{8-0} = fi;
1449 let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);
1450 let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
1452 let Inst{31} = 0x0;
1475 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1482 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
1491 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1502 VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1517 string asmName, bit single = 0> {
1521 VOP2e<op{5-0}, ps.Pfl> {
1531 VOP3e_gfx11_gfx12<{0, 1, 0, 0, op{5-0}}, ps.Pfl> {
1558 VOP2e<op{5-0}, ps.Pfl> {
1621 VOP3_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, NAME>;
1625 defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 0, 0, op{5-0}}, opName, asmName> ;
1630 VOP3be_Realtriple<Gen, {0, 1, 0, 0, op{5-0}}, /*isSingle=*/ 0, opName, asmName>,
1653 string asmName, bit isSingle = 0> {
1722 defm V_ADD_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x002, "V_ADD_F64_pseudo", "v_add_f64">;
1723 defm V_MUL_F64 : VOP2_Real_NO_DPP_with_name_gfx12<0x006, "V_MUL_F64_pseudo", "v_mul_f64">;
1724 defm V_LSHLREV_B64 : VOP2_Real_NO_DPP_with_name_gfx12<0x01f, "V_LSHLREV_B64_pseudo", "v_lshlrev_b64">;
1725 defm V_MIN_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00d, "v_min_f64">;
1726 defm V_MAX_NUM_F64 : VOP2_Real_NO_DPP_with_alias_gfx12<0x00e, "v_max_f64">;
1728 defm V_CNDMASK_B32 : VOP2e_Real_gfx12<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
1730 VOP2be_Real_gfx12<0x020, "V_ADDC_U32", "v_add_co_ci_u32">;
1732 VOP2be_Real_gfx12<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">;
1734 VOP2be_Real_gfx12<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1736 defm V_MIN_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x015, "V_MIN_F32", "v_min_num_f32">;
1737 defm V_MAX_NUM_F32 : VOP2_Real_FULL_with_name_gfx12<0x016, "V_MAX_F32", "v_max_num_f32">;
1738 defm V_MIN_NUM_F16 : VOP2_Real_FULL_t16_and_fake16_gfx12<0x030, "V_MIN_F16", "v_min_num_f16", "v_min_f16">;
1739 defm V_MAX_NUM_F16 : VOP2_Real_FULL_t16_and_fake16_gfx12<0x031, "V_MAX_F16", "v_max_num_f16", "v_max_f16">;
1764 string asmName, bit isSingle = 0> {
1837 defm V_CNDMASK_B32 : VOP2e_Real_gfx11<0x001, "V_CNDMASK_B32",
1839 defm V_DOT2ACC_F32_F16 : VOP2_Real_NO_VOP3_with_name_gfx11<0x002,
1841 defm V_FMAC_DX9_ZERO_F32 : VOP2_Real_NO_DPP_with_name_gfx11<0x006,
1843 defm V_MUL_DX9_ZERO_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x007,
1845 defm V_LSHLREV_B32 : VOP2_Real_FULL_gfx11_gfx12<0x018>;
1846 defm V_LSHRREV_B32 : VOP2_Real_FULL_gfx11_gfx12<0x019>;
1847 defm V_ASHRREV_I32 : VOP2_Real_FULL_gfx11_gfx12<0x01a>;
1849 VOP2be_Real_gfx11<0x020, "V_ADDC_U32", "v_add_co_ci_u32">;
1851 VOP2be_Real_gfx11<0x021, "V_SUBB_U32", "v_sub_co_ci_u32">;
1853 VOP2be_Real_gfx11<0x022, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
1855 defm V_CVT_PK_RTZ_F16_F32 : VOP2_Real_FULL_with_name_gfx11_gfx12<0x02f,
1857 defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx11_gfx12<0x03c>;
1859 defm V_ADD_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x032, "v_add_f16">;
1860 defm V_SUB_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x033, "v_sub_f16">;
1861 defm V_SUBREV_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x034, "v_subrev_f16">;
1862 defm V_MUL_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x035, "v_mul_f16">;
1863 defm V_FMAC_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x036, "v_fmac_f16">;
1864 defm V_LDEXP_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11_gfx12<0x03b, "v_ldexp_f16">;
1865 defm V_MAX_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11<0x039, "v_max_f16">;
1866 defm V_MIN_F16 : VOP2_Real_FULL_t16_and_fake16_gfx11<0x03a, "v_min_f16">;
1867 defm V_FMAMK_F16 : VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12<0x037, "v_fmamk_f16">;
1868 defm V_FMAAK_F16 : VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12<0x038, "v_fmaak_f16">;
1871 defm V_CNDMASK_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x25d, "v_cndmask_b16">;
1872 defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11_gfx12<0x31c>;
1873 defm V_BFM_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31d>;
1874 defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31e>;
1875 defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31f>;
1876 defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x320>;
1877 defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;
1878 defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;
1879 defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11_gfx12<0x323>;
1880 defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11_gfx12<0x324>;
1881 defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x300>;
1882 defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x301>;
1883 defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x302>;
1905 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
1911 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(opName).Pfl> {
1919 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
1924 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1930 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
1946 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
1955 VOP3e_gfx10<{0, 1, 0, 0, op{5-0}},
1966 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1992 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl> {
2000 VOP3be_gfx10<{0, 1, 0, 0, op{5-0}},
2010 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
2017 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
2026 VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
2147 defm V_FMAC_LEGACY_F32 : VOP2_Real_gfx10<0x006>;
2149 defm V_XNOR_B32 : VOP2_Real_gfx10_gfx11_gfx12<0x01e>;
2150 defm V_FMAC_F32 : VOP2_Real_gfx10_gfx11_gfx12<0x02b>;
2151 defm V_FMAMK_F32 : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02c>;
2152 defm V_FMAAK_F32 : VOP2Only_Real_MADK_gfx10_gfx11_gfx12<0x02d>;
2153 defm V_ADD_F16 : VOP2_Real_gfx10<0x032>;
2154 defm V_SUB_F16 : VOP2_Real_gfx10<0x033>;
2155 defm V_SUBREV_F16 : VOP2_Real_gfx10<0x034>;
2156 defm V_MUL_F16 : VOP2_Real_gfx10<0x035>;
2157 defm V_FMAC_F16 : VOP2_Real_gfx10<0x036>;
2158 defm V_FMAMK_F16 : VOP2Only_Real_MADK_gfx10<0x037>;
2159 defm V_FMAAK_F16 : VOP2Only_Real_MADK_gfx10<0x038>;
2160 defm V_MAX_F16 : VOP2_Real_gfx10<0x039>;
2161 defm V_MIN_F16 : VOP2_Real_gfx10<0x03a>;
2162 defm V_LDEXP_F16 : VOP2_Real_gfx10<0x03b>;
2165 defm V_PK_FMAC_F16 : VOP2_Real_e32_gfx10<0x03c>;
2170 VOP2_Real_with_name_gfx10_gfx11_gfx12<0x025, "V_ADD_U32", "v_add_nc_u32">;
2172 VOP2_Real_with_name_gfx10_gfx11_gfx12<0x026, "V_SUB_U32", "v_sub_nc_u32">;
2174 VOP2_Real_with_name_gfx10_gfx11_gfx12<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
2178 VOP2be_Real_gfx10<0x028, "V_ADDC_U32", "v_add_co_ci_u32">;
2180 VOP2be_Real_gfx10<0x029, "V_SUBB_U32", "v_sub_co_ci_u32">;
2182 VOP2be_Real_gfx10<0x02a, "V_SUBBREV_U32", "v_subrev_co_ci_u32">;
2185 VOP2e_Real_gfx10<0x001, "V_CNDMASK_B32", "v_cndmask_b32">;
2188 defm V_BFM_B32 : VOP3Only_Real_gfx10<0x363>;
2189 defm V_BCNT_U32_B32 : VOP3Only_Real_gfx10<0x364>;
2190 defm V_MBCNT_LO_U32_B32 : VOP3Only_Real_gfx10<0x365>;
2191 defm V_MBCNT_HI_U32_B32 : VOP3Only_Real_gfx10<0x366>;
2192 defm V_LDEXP_F32 : VOP3Only_Real_gfx10<0x362>;
2193 defm V_CVT_PKNORM_I16_F32 : VOP3Only_Real_gfx10<0x368>;
2194 defm V_CVT_PKNORM_U16_F32 : VOP3Only_Real_gfx10<0x369>;
2195 defm V_CVT_PK_U16_U32 : VOP3Only_Real_gfx10<0x36a>;
2196 defm V_CVT_PK_I16_I32 : VOP3Only_Real_gfx10<0x36b>;
2199 defm V_ADD_CO_U32 : VOP3beOnly_Real_gfx10<0x30f>;
2200 defm V_SUB_CO_U32 : VOP3beOnly_Real_gfx10<0x310>;
2201 defm V_SUBREV_CO_U32 : VOP3beOnly_Real_gfx10<0x319>;
2222 let Inst{8-0} = 0xfa; //dpp
2223 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
2224 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
2226 let Inst{31} = 0x0; //encoding
2233 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
2238 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
2243 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(opName#"_e32").Pfl>;
2248 VOP3e_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;
2253 VOP3be_gfx6_gfx7<{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(opName#"_e64").Pfl>;
2289 defm V_CNDMASK_B32 : VOP2_Real_gfx6_gfx7<0x000>;
2290 defm V_MIN_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00d>;
2291 defm V_MAX_LEGACY_F32 : VOP2_Real_gfx6_gfx7<0x00e>;
2292 defm V_LSHR_B32 : VOP2_Real_gfx6_gfx7<0x015>;
2293 defm V_ASHR_I32 : VOP2_Real_gfx6_gfx7<0x017>;
2294 defm V_LSHL_B32 : VOP2_Real_gfx6_gfx7<0x019>;
2295 defm V_BFM_B32 : VOP2_Real_gfx6_gfx7<0x01e>;
2296 defm V_BCNT_U32_B32 : VOP2_Real_gfx6_gfx7<0x022>;
2297 defm V_MBCNT_LO_U32_B32 : VOP2_Real_gfx6_gfx7<0x023>;
2298 defm V_MBCNT_HI_U32_B32 : VOP2_Real_gfx6_gfx7<0x024>;
2299 defm V_LDEXP_F32 : VOP2_Real_gfx6_gfx7<0x02b>;
2300 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_gfx6_gfx7<0x02c>;
2301 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_gfx6_gfx7<0x02d>;
2302 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_gfx6_gfx7<0x02e>;
2303 defm V_CVT_PK_U16_U32 : VOP2_Real_gfx6_gfx7<0x030>;
2304 defm V_CVT_PK_I16_I32 : VOP2_Real_gfx6_gfx7<0x031>;
2308 defm V_ADD_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x025, "V_ADD_CO_U32", "v_add_i32">;
2309 defm V_SUB_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x026, "V_SUB_CO_U32", "v_sub_i32">;
2310 defm V_SUBREV_I32 : VOP2be_Real_gfx6_gfx7_with_name<0x027, "V_SUBREV_CO_U32", "v_subrev_i32">;
2311 defm V_ADDC_U32 : VOP2be_Real_gfx6_gfx7<0x028>;
2312 defm V_SUBB_U32 : VOP2be_Real_gfx6_gfx7<0x029>;
2313 defm V_SUBBREV_U32 : VOP2be_Real_gfx6_gfx7<0x02a>;
2315 defm V_READLANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x001>;
2318 defm V_WRITELANE_B32 : VOP2_Lane_Real_gfx6_gfx7<0x002>;
2332 defm V_ADD_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x003>;
2333 defm V_SUB_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x004>;
2334 defm V_SUBREV_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x005>;
2335 defm V_MAC_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x006>;
2336 defm V_MUL_LEGACY_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x007>;
2337 defm V_MUL_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x008>;
2338 defm V_MUL_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x009>;
2339 defm V_MUL_HI_I32_I24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00a>;
2340 defm V_MUL_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00b>;
2341 defm V_MUL_HI_U32_U24 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x00c>;
2342 defm V_MIN_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x00f>;
2343 defm V_MAX_F32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11<0x010>;
2344 defm V_MIN_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x011>;
2345 defm V_MAX_I32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x012>;
2346 defm V_MIN_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x013>;
2347 defm V_MAX_U32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x014>;
2348 defm V_LSHRREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x016>;
2349 defm V_ASHRREV_I32 : VOP2_Real_gfx6_gfx7_gfx10<0x018>;
2350 defm V_LSHLREV_B32 : VOP2_Real_gfx6_gfx7_gfx10<0x01a>;
2351 defm V_AND_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01b>;
2352 defm V_OR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01c>;
2353 defm V_XOR_B32 : VOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x01d>;
2354 defm V_MAC_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x01f>;
2355 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_gfx6_gfx7_gfx10<0x02f>;
2356 defm V_MADMK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x020>;
2357 defm V_MADAK_F32 : VOP2Only_Real_MADK_gfx6_gfx7_gfx10<0x021>;
2367 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
2372 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl> {
2380 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
2399 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
2407 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2414 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
2422 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
2428 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
2435 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
2455 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(OpName#"_e32").Pfl> {
2461 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(OpName#"_e64").Pfl> {
2468 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(OpName#"_sdwa").Pfl> {
2484 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
2487 VOP3e_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
2491 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
2510 defm V_CNDMASK_B32 : VOP2_Real_e32e64_vi <0x0>;
2511 defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;
2512 defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;
2513 defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;
2515 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;
2516 defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;
2517 defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;
2518 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>;
2519 defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>;
2520 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>;
2521 defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>;
2522 defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>;
2523 defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>;
2524 defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>;
2525 defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>;
2526 defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>;
2527 defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>;
2528 defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>;
2529 defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>;
2530 defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>;
2531 defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>;
2532 defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>;
2533 defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>;
2534 defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>;
2535 defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>;
2537 defm V_ADD_U32 : VOP2be_Real_e32e64_vi_only <0x19, "V_ADD_CO_U32", "v_add_u32">;
2538 defm V_SUB_U32 : VOP2be_Real_e32e64_vi_only <0x1a, "V_SUB_CO_U32", "v_sub_u32">;
2539 defm V_SUBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1b, "V_SUBREV_CO_U32", "v_subrev_u32">;
2540 defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">;
2541 defm V_SUBB_U32 : VOP2be_Real_e32e64_vi_only <0x1d, "V_SUBB_U32", "v_subb_u32">;
2542 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi_only <0x1e, "V_SUBBREV_U32", "v_subbrev_u32">;
2545 defm V_ADD_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x19, "V_ADD_CO_U32", "v_add_co_u32">;
2546 defm V_SUB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1a, "V_SUB_CO_U32", "v_sub_co_u32">;
2547 defm V_SUBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1b, "V_SUBREV_CO_U32", "v_subrev_co_u32">;
2548 defm V_ADDC_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1c, "V_ADDC_U32", "v_addc_co_u32">;
2549 defm V_SUBB_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1d, "V_SUBB_U32", "v_subb_co_u32">;
2550 defm V_SUBBREV_CO_U32 : VOP2be_Real_e32e64_gfx9 <0x1e, "V_SUBBREV_U32", "v_subbrev_co_u32">;
2552 defm V_ADD_U32 : VOP2_Real_e32e64_gfx9 <0x34>;
2553 defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>;
2554 defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>;
2557 defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>;
2558 defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>;
2559 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>;
2560 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>;
2561 defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>;
2562 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
2563 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
2564 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
2565 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>;
2566 defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>;
2567 defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>;
2569 defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>;
2570 defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>;
2571 defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>;
2572 defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>;
2573 defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>;
2574 defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;
2575 defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;
2576 defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;
2577 defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;
2578 defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;
2579 defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
2580 defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
2581 defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
2582 defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;
2583 defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
2584 defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
2585 defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;
2586 defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;
2587 defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
2588 defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
2589 defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
2598 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),
2599 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))
2601 let UseInstAsmMatchConverter = 0;
2628 defm V_FMAC_F32 : VOP2_Real_e32e64_vi <0x3b>;
2629 defm V_XNOR_B32 : VOP2_Real_e32e64_vi <0x3d>;
2637 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
2648 VOP2_Real_e64_gfx90a<{0, 1, 0, 0, op{5-0}}>;
2663 defm V_FMAC_F64 : VOP2_Real_e32e64_gfx90a <0x4>;
2667 defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
2671 defm V_FMAMK_F32 : VOP2_Real_MADK_gfx940 <0x17>;
2672 defm V_FMAAK_F32 : VOP2_Real_MADK_gfx940 <0x18>;
2692 defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
2695 defm V_DOT2C_F32_F16 : VOP2Only_Real_DOT_ACC_gfx10<0x02>;
2699 defm V_DOT4C_I32_I8 : VOP2_Real_DOT_ACC_gfx9<0x39>;
2700 defm V_DOT4C_I32_I8 : VOP2Only_Real_DOT_ACC_gfx10<0x0d>;
2704 defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
2707 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx9<0x3a>;
2711 defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
2717 defm V_DOT8C_I32_I4 : VOP2_Real_DOT_ACC_gfx10<0x02>;
2722 defm V_DOT2C_F32_BF16 : VOP2_Real_DOT_ACC_gfx9<0x16>;