Lines Matching defs:setRegister

63     setRegister(Key->getZExtValue(), Val->getZExtValue());
81     setRegister(Data[I * 2], Data[I * 2 + 1]);
138   setRegister(getRsrc1Reg(CC), Val);
143   setRegister(getRsrc1Reg(CC), Val, Ctx);
149   setRegister(getRsrc1Reg(CC) + 1, Val);
154   setRegister(getRsrc1Reg(CC) + 1, Val, Ctx);
160   setRegister(PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
166   setRegister(PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
183 void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
198 void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val,
212     // setRegister(unsigned, unsigned) could've been called while the
222     // Default to uint64_t 0 so additional calls to setRegister will allow
249     setRegister(NumUsedVgprsKey, Val);
263     setRegister(NumUsedVgprsKey, Val, Ctx);
288     setRegister(NumUsedSgprsKey, Val);
302     setRegister(NumUsedSgprsKey, Val, Ctx);
313     setRegister(getScratchSizeKey(CC), Val);
324     setRegister(getScratchSizeKey(CC), Val, Ctx);
375     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
378     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
381     setRegister(PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
384     setRegister(PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
387     setRegister(PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,