Lines Matching defs:STI
167 /// \returns True if \p STI is AMDHSA.
168 bool isHsaAbi(const MCSubtargetInfo &STI) {
169 return STI.getTargetTriple().getOS() == Triple::AMDHSA;
806 AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI)
807 : STI(STI), XnackSetting(TargetIDSetting::Any),
809 if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
811 if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
899 auto TargetTriple = STI.getTargetTriple();
900 auto Version = getIsaVersion(STI.getCPU());
912 Processor = STI.getCPU().str();
919 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) {
937 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
938 if (STI->getFeatureBits().test(FeatureWavefrontSize16))
940 if (STI->getFeatureBits().test(FeatureWavefrontSize32))
946 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
947 unsigned BytesPerCU = getAddressableLocalMemorySize(STI);
952 if (isGFX10Plus(*STI) && !STI->getFeatureBits().test(FeatureCuMode))
958 unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI) {
959 if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize32768))
961 if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize65536))
963 if (STI->getFeatureBits().test(FeatureAddressableLocalMemorySize163840))
968 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
972 if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
979 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
982 if (STI->getTargetTriple().getArch() != Triple::amdgcn)
984 unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
985 unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
992 if (isGFX10Plus(*STI) && !STI->getFeatureBits().test(FeatureCuMode))
998 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
1002 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
1004 if (isGFX90A(*STI))
1006 if (!isGFX10Plus(*STI))
1008 return hasGFX10_3Insts(*STI) ? 16 : 20;
1011 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
1013 return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
1014 getEUsPerCU(STI));
1017 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) {
1021 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) {
1026 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
1028 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
1031 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
1032 IsaVersion Version = getIsaVersion(STI->getCPU());
1034 return getAddressableNumSGPRs(STI);
1040 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI) {
1044 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
1045 IsaVersion Version = getIsaVersion(STI->getCPU());
1051 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI) {
1052 if (STI->getFeatureBits().test(FeatureSGPRInitBug))
1055 IsaVersion Version = getIsaVersion(STI->getCPU());
1063 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1066 IsaVersion Version = getIsaVersion(STI->getCPU());
1070 if (WavesPerEU >= getMaxWavesPerEU(STI))
1073 unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
1074 if (STI->getFeatureBits().test(FeatureTrapHandler))
1076 MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
1077 return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
1080 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
1084 unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
1085 IsaVersion Version = getIsaVersion(STI->getCPU());
1090 unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
1091 if (STI->getFeatureBits().test(FeatureTrapHandler))
1093 MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
1097 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
1103 IsaVersion Version = getIsaVersion(STI->getCPU());
1115 STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
1122 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
1124 return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
1125 STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
1133 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
1135 return getGranulatedNumRegisterBlocks(NumSGPRs, getSGPREncodingGranule(STI)) -
1139 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
1141 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1146 STI->getFeatureBits().test(FeatureWavefrontSize32);
1148 if (STI->getFeatureBits().test(Feature1_5xVGPRs))
1151 if (hasGFX10_3Insts(*STI))
1157 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
1159 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1164 STI->getFeatureBits().test(FeatureWavefrontSize32);
1169 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
1170 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1172 if (!isGFX10Plus(*STI))
1174 bool IsWave32 = STI->getFeatureBits().test(FeatureWavefrontSize32);
1175 if (STI->getFeatureBits().test(Feature1_5xVGPRs))
1180 unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { return 256; }
1182 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI) {
1183 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1185 return getAddressableNumArchVGPRs(STI);
1188 unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI,
1190 return getNumWavesPerEUWithNumVGPRs(NumVGPRs, getVGPRAllocGranule(STI),
1191 getMaxWavesPerEU(STI),
1192 getTotalNumVGPRs(STI));
1231 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1234 unsigned MaxWavesPerEU = getMaxWavesPerEU(STI);
1238 unsigned TotNumVGPRs = getTotalNumVGPRs(STI);
1239 unsigned AddrsableNumVGPRs = getAddressableNumVGPRs(STI);
1240 unsigned Granule = getVGPRAllocGranule(STI);
1246 unsigned MinWavesPerEU = getNumWavesPerEUWithNumVGPRs(STI, AddrsableNumVGPRs);
1248 return getMinNumVGPRs(STI, MinWavesPerEU);
1255 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1258 unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
1259 getVGPRAllocGranule(STI));
1260 unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
1264 unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
1267 NumVGPRs, getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
1271 unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI,
1275 NumVGPRs, getVGPRAllocGranule(STI, EnableWavefrontSize32));
1280 const MCSubtargetInfo *STI) {
1281 IsaVersion Version = getIsaVersion(STI->getCPU());
1289 if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
1308 S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
1604 const MCSubtargetInfo &STI) {
1608 if (Op.isSupported(STI))
1617 const MCSubtargetInfo &STI) {
1622 if (!Op.isSupported(STI))
1636 const MCSubtargetInfo &STI) {
1639 if (Op.isSupported(STI)) {
1660 const MCSubtargetInfo &STI) {
1665 if (!Op.isSupported(STI)) {
1685 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI) {
1688 Default = getDefaultCustomOperandEncoding(DepCtrInfo, DEP_CTR_SIZE, STI);
1693 const MCSubtargetInfo &STI) {
1695 HasNonDefaultVal, STI);
1699 bool &IsDefault, const MCSubtargetInfo &STI) {
1701 IsDefault, STI);
1705 const MCSubtargetInfo &STI) {
1707 STI);
1804 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1807 return !isGFX11Plus(STI);
1810 return isGFX10Plus(STI);
1813 return isGFX11Plus(STI);
1816 return !isGFX11Plus(STI);
1842 static StringLiteral const *getNfmtLookupTable(const MCSubtargetInfo &STI) {
1843 if (isSI(STI) || isCI(STI))
1845 if (isVI(STI) || isGFX9(STI))
1850 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1851 const auto *lookupTable = getNfmtLookupTable(STI);
1859 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1861 return getNfmtLookupTable(STI)[Id];
1864 bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1868 return isValidNfmt(Nfmt, STI);
1871 bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1872 return !getNfmtName(Id, STI).empty();
1884 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI) {
1885 if (isGFX11Plus(STI)) {
1899 StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI) {
1900 if(isValidUnifiedFormat(Id, STI))
1901 return isGFX10(STI) ? UfmtSymbolicGFX10[Id] : UfmtSymbolicGFX11[Id];
1905 bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI) {
1906 return isGFX10(STI) ? Id <= UfmtGFX10::UFMT_LAST : Id <= UfmtGFX11::UFMT_LAST;
1910 const MCSubtargetInfo &STI) {
1912 if (isGFX11Plus(STI)) {
1926 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1927 return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1930 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI) {
1931 if (isGFX10Plus(STI))
1944 static uint64_t getMsgIdMask(const MCSubtargetInfo &STI) {
1945 return isGFX11Plus(STI) ? ID_MASK_GFX11Plus_ : ID_MASK_PreGFX11_;
1948 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI) {
1949 return (MsgId & ~(getMsgIdMask(STI))) == 0;
1952 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1954 assert(isValidMsgId(MsgId, STI));
1959 if (msgRequiresOp(MsgId, STI)) {
1963 return !getMsgOpName(MsgId, OpId, STI).empty();
1970 const MCSubtargetInfo &STI, bool Strict) {
1971 assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1976 if (!isGFX11Plus(STI)) {
1989 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
1991 (!isGFX11Plus(STI) &&
1996 const MCSubtargetInfo &STI) {
1997 return !isGFX11Plus(STI) &&
2003 uint16_t &StreamId, const MCSubtargetInfo &STI) {
2004 MsgId = Val & getMsgIdMask(STI);
2005 if (isGFX11Plus(STI)) {
2106 bool hasXNACK(const MCSubtargetInfo &STI) {
2107 return STI.hasFeature(AMDGPU::FeatureXNACK);
2110 bool hasSRAMECC(const MCSubtargetInfo &STI) {
2111 return STI.hasFeature(AMDGPU::FeatureSRAMECC);
2114 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
2115 return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
2118 bool hasA16(const MCSubtargetInfo &STI) {
2119 return STI.hasFeature(AMDGPU::FeatureA16);
2122 bool hasG16(const MCSubtargetInfo &STI) {
2123 return STI.hasFeature(AMDGPU::FeatureG16);
2126 bool hasPackedD16(const MCSubtargetInfo &STI) {
2127 return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !isCI(STI) &&
2128 !isSI(STI);
2131 bool hasGDS(const MCSubtargetInfo &STI) {
2132 return STI.hasFeature(AMDGPU::FeatureGDS);
2135 unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler) {
2136 auto Version = getIsaVersion(STI.getCPU());
2146 unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI) { return 16; }
2148 bool isSI(const MCSubtargetInfo &STI) {
2149 return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
2152 bool isCI(const MCSubtargetInfo &STI) {
2153 return STI.hasFeature(AMDGPU::FeatureSeaIslands);
2156 bool isVI(const MCSubtargetInfo &STI) {
2157 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2160 bool isGFX9(const MCSubtargetInfo &STI) {
2161 return STI.hasFeature(AMDGPU::FeatureGFX9);
2164 bool isGFX9_GFX10(const MCSubtargetInfo &STI) {
2165 return isGFX9(STI) || isGFX10(STI);
2168 bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI) {
2169 return isGFX9(STI) || isGFX10(STI) || isGFX11(STI);
2172 bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI) {
2173 return isVI(STI) || isGFX9(STI) || isGFX10(STI);
2176 bool isGFX8Plus(const MCSubtargetInfo &STI) {
2177 return isVI(STI) || isGFX9Plus(STI);
2180 bool isGFX9Plus(const MCSubtargetInfo &STI) {
2181 return isGFX9(STI) || isGFX10Plus(STI);
2184 bool isNotGFX9Plus(const MCSubtargetInfo &STI) { return !isGFX9Plus(STI); }
2186 bool isGFX10(const MCSubtargetInfo &STI) {
2187 return STI.hasFeature(AMDGPU::FeatureGFX10);
2190 bool isGFX10_GFX11(const MCSubtargetInfo &STI) {
2191 return isGFX10(STI) || isGFX11(STI);
2194 bool isGFX10Plus(const MCSubtargetInfo &STI) {
2195 return isGFX10(STI) || isGFX11Plus(STI);
2198 bool isGFX11(const MCSubtargetInfo &STI) {
2199 return STI.hasFeature(AMDGPU::FeatureGFX11);
2202 bool isGFX11Plus(const MCSubtargetInfo &STI) {
2203 return isGFX11(STI) || isGFX12Plus(STI);
2206 bool isGFX12(const MCSubtargetInfo &STI) {
2207 return STI.getFeatureBits()[AMDGPU::FeatureGFX12];
2210 bool isGFX12Plus(const MCSubtargetInfo &STI) { return isGFX12(STI); }
2212 bool isNotGFX12Plus(const MCSubtargetInfo &STI) { return !isGFX12Plus(STI); }
2214 bool isNotGFX11Plus(const MCSubtargetInfo &STI) {
2215 return !isGFX11Plus(STI);
2218 bool isNotGFX10Plus(const MCSubtargetInfo &STI) {
2219 return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
2222 bool isGFX10Before1030(const MCSubtargetInfo &STI) {
2223 return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
2226 bool isGCN3Encoding(const MCSubtargetInfo &STI) {
2227 return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
2230 bool isGFX10_AEncoding(const MCSubtargetInfo &STI) {
2231 return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2234 bool isGFX10_BEncoding(const MCSubtargetInfo &STI) {
2235 return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2238 bool hasGFX10_3Insts(const MCSubtargetInfo &STI) {
2239 return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
2242 bool isGFX10_3_GFX11(const MCSubtargetInfo &STI) {
2243 return isGFX10_BEncoding(STI) && !isGFX12Plus(STI);
2246 bool isGFX90A(const MCSubtargetInfo &STI) {
2247 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2250 bool isGFX940(const MCSubtargetInfo &STI) {
2251 return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
2254 bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) {
2255 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2258 bool hasMAIInsts(const MCSubtargetInfo &STI) {
2259 return STI.hasFeature(AMDGPU::FeatureMAIInsts);
2262 bool hasVOPD(const MCSubtargetInfo &STI) {
2263 return STI.hasFeature(AMDGPU::FeatureVOPD);
2266 bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI) {
2267 return STI.hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2270 unsigned hasKernargPreload(const MCSubtargetInfo &STI) {
2271 return STI.hasFeature(AMDGPU::FeatureKernargPreload);
2337 assert(!isSI(STI)); \
2338 case node: return isCI(STI) ? node##_ci : node##_vi;
2341 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2344 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2347 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2349 MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI) {
2350 if (STI.getTargetTriple().getArch() == Triple::r600)
2988 const MCSubtargetInfo &STI) {
2989 return isGFX11Plus(STI)
2992 : isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2999 const MCSubtargetInfo &STI) {
3000 return isGFX11Plus(STI) ? getGfx11PlusBufferFormatInfo(Format)
3001 : isGFX10(STI) ? getGfx10BufferFormatInfo(Format)