Lines Matching defs:AMDGPU
1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
10 #include "AMDGPU.h"
37 llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5),
159 namespace AMDGPU {
222 return AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET;
236 return AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET;
247 return AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET;
258 return AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET;
563 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
565 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
583 return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X);
587 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
588 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
589 Opc == AMDGPU::V_MAC_F32_e64_vi ||
590 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
591 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
592 Opc == AMDGPU::V_MAC_F16_e64_vi ||
593 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
594 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
595 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
596 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
597 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
598 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
599 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
600 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
601 Opc == AMDGPU::V_FMAC_F16_fake16_e64_gfx11 ||
602 Opc == AMDGPU::V_FMAC_F16_fake16_e64_gfx12 ||
603 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
604 Opc == AMDGPU::V_DOT2C_F32_BF16_e64_vi ||
605 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
606 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
607 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
611 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
612 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
613 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
614 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
615 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
616 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
617 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
618 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
622 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
623 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
624 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
625 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
626 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
627 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
628 Opc == AMDGPU::V_CVT_PK_F32_BF8_fake16_e64_gfx12 ||
629 Opc == AMDGPU::V_CVT_PK_F32_FP8_fake16_e64_gfx12 ||
630 Opc == AMDGPU::V_CVT_PK_F32_BF8_t16_e64_gfx12 ||
631 Opc == AMDGPU::V_CVT_PK_F32_FP8_t16_e64_gfx12;
635 return Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
636 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
637 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
638 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
639 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
640 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
641 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
642 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
643 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
644 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
645 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
646 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
647 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
648 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
649 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
650 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
651 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
720 if (OpDesc.operands()[CompOprIdx].OperandType == AMDGPU::OPERAND_KIMM32) {
1115 STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
1125 STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
2103 return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv());
2107 return STI.hasFeature(AMDGPU::FeatureXNACK);
2111 return STI.hasFeature(AMDGPU::FeatureSRAMECC);
2115 return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
2119 return STI.hasFeature(AMDGPU::FeatureA16);
2123 return STI.hasFeature(AMDGPU::FeatureG16);
2127 return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !isCI(STI) &&
2132 return STI.hasFeature(AMDGPU::FeatureGDS);
2149 return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
2153 return STI.hasFeature(AMDGPU::FeatureSeaIslands);
2157 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2161 return STI.hasFeature(AMDGPU::FeatureGFX9);
2187 return STI.hasFeature(AMDGPU::FeatureGFX10);
2199 return STI.hasFeature(AMDGPU::FeatureGFX11);
2207 return STI.getFeatureBits()[AMDGPU::FeatureGFX12];
2223 return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
2227 return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
2231 return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2235 return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2239 return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
2247 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2251 return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
2255 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2259 return STI.hasFeature(AMDGPU::FeatureMAIInsts);
2263 return STI.hasFeature(AMDGPU::FeatureVOPD);
2267 return STI.hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2271 return STI.hasFeature(AMDGPU::FeatureKernargPreload);
2282 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
2283 const MCRegister FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
2285 Reg == AMDGPU::SCC;
2289 return MRI.getEncodingValue(Reg) & AMDGPU::HWEncoding::IS_HI16;
2293 using namespace AMDGPU; \
2369 case AMDGPU::SRC_SHARED_BASE_LO:
2370 case AMDGPU::SRC_SHARED_BASE:
2371 case AMDGPU::SRC_SHARED_LIMIT_LO:
2372 case AMDGPU::SRC_SHARED_LIMIT:
2373 case AMDGPU::SRC_PRIVATE_BASE_LO:
2374 case AMDGPU::SRC_PRIVATE_BASE:
2375 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2376 case AMDGPU::SRC_PRIVATE_LIMIT:
2377 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2379 case AMDGPU::SRC_VCCZ:
2380 case AMDGPU::SRC_EXECZ:
2381 case AMDGPU::SRC_SCC:
2383 case AMDGPU::SGPR_NULL:
2399 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
2400 OpType <= AMDGPU::OPERAND_SRC_LAST;
2406 return OpType >= AMDGPU::OPERAND_KIMM_FIRST &&
2407 OpType <= AMDGPU::OPERAND_KIMM_LAST;
2414 case AMDGPU::OPERAND_REG_IMM_FP32:
2415 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
2416 case AMDGPU::OPERAND_REG_IMM_FP64:
2417 case AMDGPU::OPERAND_REG_IMM_FP16:
2418 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
2419 case AMDGPU::OPERAND_REG_IMM_V2FP16:
2420 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
2421 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2422 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
2423 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2424 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
2425 case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
2426 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
2427 case AMDGPU::OPERAND_REG_IMM_V2FP32:
2428 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
2429 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2439 return (OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
2440 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST) ||
2441 (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST &&
2442 OpType <= AMDGPU::OPERAND_REG_INLINE_AC_LAST);
2449 case AMDGPU::SGPR_LO16RegClassID:
2450 case AMDGPU::AGPR_LO16RegClassID:
2452 case AMDGPU::SGPR_32RegClassID:
2453 case AMDGPU::VGPR_32RegClassID:
2454 case AMDGPU::VRegOrLds_32RegClassID:
2455 case AMDGPU::AGPR_32RegClassID:
2456 case AMDGPU::VS_32RegClassID:
2457 case AMDGPU::AV_32RegClassID:
2458 case AMDGPU::SReg_32RegClassID:
2459 case AMDGPU::SReg_32_XM0RegClassID:
2460 case AMDGPU::SRegOrLds_32RegClassID:
2462 case AMDGPU::SGPR_64RegClassID:
2463 case AMDGPU::VS_64RegClassID:
2464 case AMDGPU::SReg_64RegClassID:
2465 case AMDGPU::VReg_64RegClassID:
2466 case AMDGPU::AReg_64RegClassID:
2467 case AMDGPU::SReg_64_XEXECRegClassID:
2468 case AMDGPU::VReg_64_Align2RegClassID:
2469 case AMDGPU::AReg_64_Align2RegClassID:
2470 case AMDGPU::AV_64RegClassID:
2471 case AMDGPU::AV_64_Align2RegClassID:
2473 case AMDGPU::SGPR_96RegClassID:
2474 case AMDGPU::SReg_96RegClassID:
2475 case AMDGPU::VReg_96RegClassID:
2476 case AMDGPU::AReg_96RegClassID:
2477 case AMDGPU::VReg_96_Align2RegClassID:
2478 case AMDGPU::AReg_96_Align2RegClassID:
2479 case AMDGPU::AV_96RegClassID:
2480 case AMDGPU::AV_96_Align2RegClassID:
2482 case AMDGPU::SGPR_128RegClassID:
2483 case AMDGPU::SReg_128RegClassID:
2484 case AMDGPU::VReg_128RegClassID:
2485 case AMDGPU::AReg_128RegClassID:
2486 case AMDGPU::VReg_128_Align2RegClassID:
2487 case AMDGPU::AReg_128_Align2RegClassID:
2488 case AMDGPU::AV_128RegClassID:
2489 case AMDGPU::AV_128_Align2RegClassID:
2490 case AMDGPU::SReg_128_XNULLRegClassID:
2492 case AMDGPU::SGPR_160RegClassID:
2493 case AMDGPU::SReg_160RegClassID:
2494 case AMDGPU::VReg_160RegClassID:
2495 case AMDGPU::AReg_160RegClassID:
2496 case AMDGPU::VReg_160_Align2RegClassID:
2497 case AMDGPU::AReg_160_Align2RegClassID:
2498 case AMDGPU::AV_160RegClassID:
2499 case AMDGPU::AV_160_Align2RegClassID:
2501 case AMDGPU::SGPR_192RegClassID:
2502 case AMDGPU::SReg_192RegClassID:
2503 case AMDGPU::VReg_192RegClassID:
2504 case AMDGPU::AReg_192RegClassID:
2505 case AMDGPU::VReg_192_Align2RegClassID:
2506 case AMDGPU::AReg_192_Align2RegClassID:
2507 case AMDGPU::AV_192RegClassID:
2508 case AMDGPU::AV_192_Align2RegClassID:
2510 case AMDGPU::SGPR_224RegClassID:
2511 case AMDGPU::SReg_224RegClassID:
2512 case AMDGPU::VReg_224RegClassID:
2513 case AMDGPU::AReg_224RegClassID:
2514 case AMDGPU::VReg_224_Align2RegClassID:
2515 case AMDGPU::AReg_224_Align2RegClassID:
2516 case AMDGPU::AV_224RegClassID:
2517 case AMDGPU::AV_224_Align2RegClassID:
2519 case AMDGPU::SGPR_256RegClassID:
2520 case AMDGPU::SReg_256RegClassID:
2521 case AMDGPU::VReg_256RegClassID:
2522 case AMDGPU::AReg_256RegClassID:
2523 case AMDGPU::VReg_256_Align2RegClassID:
2524 case AMDGPU::AReg_256_Align2RegClassID:
2525 case AMDGPU::AV_256RegClassID:
2526 case AMDGPU::AV_256_Align2RegClassID:
2527 case AMDGPU::SReg_256_XNULLRegClassID:
2529 case AMDGPU::SGPR_288RegClassID:
2530 case AMDGPU::SReg_288RegClassID:
2531 case AMDGPU::VReg_288RegClassID:
2532 case AMDGPU::AReg_288RegClassID:
2533 case AMDGPU::VReg_288_Align2RegClassID:
2534 case AMDGPU::AReg_288_Align2RegClassID:
2535 case AMDGPU::AV_288RegClassID:
2536 case AMDGPU::AV_288_Align2RegClassID:
2538 case AMDGPU::SGPR_320RegClassID:
2539 case AMDGPU::SReg_320RegClassID:
2540 case AMDGPU::VReg_320RegClassID:
2541 case AMDGPU::AReg_320RegClassID:
2542 case AMDGPU::VReg_320_Align2RegClassID:
2543 case AMDGPU::AReg_320_Align2RegClassID:
2544 case AMDGPU::AV_320RegClassID:
2545 case AMDGPU::AV_320_Align2RegClassID:
2547 case AMDGPU::SGPR_352RegClassID:
2548 case AMDGPU::SReg_352RegClassID:
2549 case AMDGPU::VReg_352RegClassID:
2550 case AMDGPU::AReg_352RegClassID:
2551 case AMDGPU::VReg_352_Align2RegClassID:
2552 case AMDGPU::AReg_352_Align2RegClassID:
2553 case AMDGPU::AV_352RegClassID:
2554 case AMDGPU::AV_352_Align2RegClassID:
2556 case AMDGPU::SGPR_384RegClassID:
2557 case AMDGPU::SReg_384RegClassID:
2558 case AMDGPU::VReg_384RegClassID:
2559 case AMDGPU::AReg_384RegClassID:
2560 case AMDGPU::VReg_384_Align2RegClassID:
2561 case AMDGPU::AReg_384_Align2RegClassID:
2562 case AMDGPU::AV_384RegClassID:
2563 case AMDGPU::AV_384_Align2RegClassID:
2565 case AMDGPU::SGPR_512RegClassID:
2566 case AMDGPU::SReg_512RegClassID:
2567 case AMDGPU::VReg_512RegClassID:
2568 case AMDGPU::AReg_512RegClassID:
2569 case AMDGPU::VReg_512_Align2RegClassID:
2570 case AMDGPU::AReg_512_Align2RegClassID:
2571 case AMDGPU::AV_512RegClassID:
2572 case AMDGPU::AV_512_Align2RegClassID:
2574 case AMDGPU::SGPR_1024RegClassID:
2575 case AMDGPU::SReg_1024RegClassID:
2576 case AMDGPU::VReg_1024RegClassID:
2577 case AMDGPU::AReg_1024RegClassID:
2578 case AMDGPU::VReg_1024_Align2RegClassID:
2579 case AMDGPU::AReg_1024_Align2RegClassID:
2580 case AMDGPU::AV_1024RegClassID:
2581 case AMDGPU::AV_1024_Align2RegClassID:
2776 case AMDGPU::OPERAND_REG_IMM_V2INT16:
2777 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2778 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
2780 case AMDGPU::OPERAND_REG_IMM_V2FP16:
2781 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2782 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
2784 case AMDGPU::OPERAND_REG_IMM_V2BF16:
2785 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
2786 case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:
2947 if (AMDGPU::isGFX10(ST))
2950 if (AMDGPU::isGFX12(ST))
3012 if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID ||
3013 OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
3029 } // namespace AMDGPU
3032 const AMDGPU::IsaInfo::TargetIDSetting S) {
3034 case (AMDGPU::IsaInfo::TargetIDSetting::Unsupported):
3037 case (AMDGPU::IsaInfo::TargetIDSetting::Any):
3040 case (AMDGPU::IsaInfo::TargetIDSetting::Off):
3043 case (AMDGPU::IsaInfo::TargetIDSetting::On):