Lines Matching defs:ValueReg

1408                                            unsigned ValueReg, bool IsKill) {
1422   unsigned Dst = IsStore ? Reg : ValueReg;
1423   unsigned Src = IsStore ? ValueReg : Reg;
1426   if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) {
1523     unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1541   const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);
1735             ? ValueReg
1736             : Register(getSubReg(ValueReg,
1769              ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
1770              : ValueReg;
1775         MIB.addReg(ValueReg, RegState::ImplicitDefine);
1785         MIB.addReg(ValueReg, RegState::Implicit | State);
1797       SubReg = Register(getSubReg(ValueReg,
1818           AccRead.addReg(ValueReg, RegState::ImplicitDefine);
1820           AccRead.addReg(ValueReg, RegState::Implicit);
1873       MIB.addReg(ValueReg, RegState::ImplicitDefine);
1883       MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);