Lines Matching defs:VGPR
57 // This is mostly to spill SGPRs to memory. Spilling SGPRs into VGPR lanes emits
60 // When spilling to memory, the SGPRs are written into VGPR lanes and the VGPR
62 // For this, a VGPR is required where the needed lanes can be clobbered. The
63 // RegScavenger can provide a VGPR where currently active lanes can be
67 // - Try to scavenge VGPR
94 // The SGPRs are written into this VGPR, which is then written to scratch
158 // Tries to scavenge SGPRs to save EXEC and a VGPR. Uses v0 if no VGPR is
163 // buffer_store_dword v1 ; Write scavenged VGPR to emergency slot
166 // buffer_store_dword v0 ; Only if no free VGPR was found
172 // Scavenged temporary VGPR to use. It must be scavenged once for any number
177 // used lanes of the chosen VGPR.
245 // buffer_load_dword v1 ; Write scavenged VGPR to emergency slot
246 // s_waitcnt vmcnt(0) ; If a free VGPR was found
251 // s_waitcnt vmcnt(0) ; If a free VGPR was found
253 // buffer_load_dword v0 ; Only if no free VGPR was found
452 bool SIRegisterInfo::isChainScratchRegister(Register VGPR) {
453 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8;
585 // TODO: it shall be possible to estimate maximum AGPR/VGPR pressure and split
673 // TODO: May need to reserve a VGPR if doing LDS spilling.
738 // VGPR available at all times.
743 // During wwm-regalloc, reserve the registers for perlane VGPR allocation. The
1445 // This differs from buildSpillLoadStore by only scavenging a VGPR. It does not
1542 // On gfx90a+ AGPR is a regular VGPR acceptable for loads and stores.
1547 // a temporary VGPR.
1568 "unexpected VGPR spill offset");
1570 // Track a VGPR to use for a constant offset we need to materialize.
1573 // Track a VGPR to use as an intermediate value.
1577 // Materialize a VGPR offset required for the given SGPR/VGPR/Immediate
1581 // We are using a VGPR offset
1583 // We only have 1 VGPR offset, or 1 SGPR offset. We don't have a free
1653 // VGPRs too. Since we need a VGPR in order to spill SGPRs (this is true
1661 // to use the VGPR offset is fewer instructions.
1680 // We are using a VGPR offset
1725 // offset and need to use a VGPR offset, we ideally have at least 2
1726 // scratch VGPRs. If we don't have a second free VGPR without spilling,
1727 // recycle the VGPR used for the offset which requires resetting after
1761 // change. For targets with VGPR alignment requirement this is important
1842 // For an AGPR spill, we reuse the same temp VGPR for the offset and the
1924 // Load/store VGPR
1949 // This only ever adds one VGPR spill
1976 // VGPR lanes (mapped from spill stack slot) may be shared for SGPR
1977 // spills of different sizes. This accounts for number of VGPR lanes alloted
1981 "the VGPR lanes.");
1998 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR)
2001 .addReg(Spill.VGPR);
2028 // Per VGPR helper data
2034 // Write sub registers into the VGPR
2069 // Write out VGPR
2108 .addReg(Spill.VGPR)
2122 // Per VGPR helper data
2126 // Load in VGPR data
2176 // Write sub registers into the VGPR
2202 // Don't need to write VGPR out.
2210 // Don't need to load VGPR in.
2235 /// a VGPR and the stack slot can be safely eliminated when all other users are
2335 // VGPR register spill
2560 // register, but may have a VGPR only operand.
2591 // If we know we have a VGPR already, it's more likely the other
2863 // a VGPR.
2899 // TODO: for flat scratch another attempt can be made with a VGPR index
3725 // VGPR tuples have an alignment requirement on gfx90a variants.