Lines Matching defs:LoadStoreOp

1458   int LoadStoreOp = IsStore ?
1460   if (LoadStoreOp == -1)
1468       BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
1485                                           unsigned LoadStoreOp,
1487   bool IsStore = TII->get(LoadStoreOp).mayStore();
1488   bool HasVAddr = AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::vaddr);
1490       !HasVAddr && !AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::saddr);
1494     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1498     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1502     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR
1506     LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR
1514     LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp);
1516     LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1518   return LoadStoreOp;
1523     unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1533   const MCInstrDesc *Desc = &TII->get(LoadStoreOp);
1535   bool IsFlat = TII->isFLATScratch(LoadStoreOp);
1560     LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1561     Desc = &TII->get(LoadStoreOp);
1696     assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0
1700       LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp);
1703       LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp);
1706     Desc = &TII->get(LoadStoreOp);
1713       LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
1715     Desc = &TII->get(LoadStoreOp);
1718       int NewLoadStoreOp = IsStore ? getOffenMUBUFStore(LoadStoreOp)
1719                                    : getOffenMUBUFLoad(LoadStoreOp);
1799       unsigned Opc = getFlatScratchSpillOpcode(TII, LoadStoreOp, RemEltSize);