Lines Matching defs:IsKill

90   bool IsKill;
126                    bool IsKill, int Index, RegScavenger *RS)
127       : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()),
234                                     /*IsKill*/ false);
258                                   /*IsKill*/ false);
270                                   /*IsKill*/ false);
309                                   /*IsKill*/ false);
1408                                            unsigned ValueReg, bool IsKill) {
1432                        .addReg(Src, getKillRegState(IsKill));
1440                  .addReg(Src, getKillRegState(IsKill));
1523     unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1746       SrcDstRegState |= getKillRegState(IsKill);
1771       auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill);
1816                            .addReg(SubReg, getKillRegState(IsKill));
1839             .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));
1923                                              bool IsKill) const {
1947     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
1992       bool UseKill = SB.IsKill && IsLastSubreg;
2026     unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
2064             SuperKillState |= getKillRegState(SB.IsKill);
2172   unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill);
2198           SuperKillState |= getKillRegState(SB.IsKill);