Lines Matching defs:FIOp

984     MachineOperand *FIOp = &MI.getOperand(2);
986     if (!FIOp->isFI())
987       std::swap(FIOp, ImmOp);
991       FIOp->ChangeToRegister(BaseReg, false);
1030     MachineOperand *FIOp = &MI.getOperand(Src0Idx);
1032     if (!FIOp->isFI())
1033       std::swap(FIOp, ImmOp);
1036       FIOp->ChangeToRegister(BaseReg, false);
1050       FIOp->ChangeToRegister(BaseReg, false);
1075   MachineOperand *FIOp =
1082   assert(FIOp && FIOp->isFI() && "frame index must be address operand");
1089     FIOp->ChangeToRegister(BaseReg, false);
1101   FIOp->ChangeToRegister(BaseReg, false);
2291   MachineOperand *FIOp = &MI->getOperand(FIOperandNum);
2615         FIOp->ChangeToImmediate(Offset);
2619         FIOp->ChangeToImmediate(Offset);
2650         FIOp->ChangeToImmediate(0);
2655         std::swap(FIOp, OtherOp);
2686       if (FIOp->isImm() && FIOp->getImm() == 0 && DeadVCC && !HasClamp) {
2742           FIOp->ChangeToRegister(MaterializedReg, false);
2744           FIOp->ChangeToImmediate(0);
2768         FIOp->ChangeToImmediate(Offset);
2772         FIOp->ChangeToImmediate(Offset);
2779         MI->setDesc(TII->get(FIOp->isReg() ? AMDGPU::COPY : AMDGPU::S_MOV_B32));
2780       } else if (DeadSCC && FIOp->isImm() && FIOp->getImm() == 0) {
2788       assert(!FIOp->isFI());
2805           FIOp->ChangeToRegister(FrameReg, false);
2857         FIOp->ChangeToImmediate(Offset);
2858         if (TII->isImmOperandLegal(*MI, FIOperandNum, *FIOp))
2864       FIOp->ChangeToRegister(AMDGPU::M0, false);
2865       bool UseSGPR = TII->isOperandLegal(*MI, FIOperandNum, FIOp);
2868         FIOp->setReg(FrameReg);
2877       FIOp->setReg(TmpReg);
2878       FIOp->setIsKill();
2907         FIOp->setReg(FrameReg);
2908         FIOp->setIsKill(false);
3154       FIOp->ChangeToRegister(ResultReg, false, false, true);
3185     FIOp->ChangeToImmediate(Offset);
3186     if (!TII->isImmOperandLegal(*MI, FIOperandNum, *FIOp)) {
3191       FIOp->ChangeToRegister(TmpReg, false, false, true);