Lines Matching defs:SU
176 void SIScheduleBlock::addUnit(SUnit *SU) {
177 NodeNum2Index[SU->NodeNum] = SUnits.size();
178 SUnits.push_back(SU);
184 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
236 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
244 for (SUnit* SU : TopReadySUs) {
249 TryCand.SU = SU;
250 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure);
253 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum];
254 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum];
256 HasLowLatencyNonWaitedParent[NodeNum2Index[SU->NodeNum]];
262 return TopCand.SU;
272 for (SUnit* SU : SUnits) {
273 if (!SU->NumPredsLeft)
274 TopReadySUs.push_back(SU);
278 SUnit *SU = TopReadySUs[0];
279 ScheduledSUnits.push_back(SU);
280 nodeScheduled(SU);
313 // Goes though all SU. RPTracker captures what had to be alive for the SUs
315 for (SUnit* SU : ScheduledSUnits) {
316 RPTracker.setPos(SU->getInstr());
389 for (SUnit* SU : SUnits) {
390 if (!SU->NumPredsLeft)
391 TopReadySUs.push_back(SU);
395 SUnit *SU = pickNode();
396 ScheduledSUnits.push_back(SU);
397 TopRPTracker.setPos(SU->getInstr());
399 nodeScheduled(SU);
409 for (SUnit* SU : SUnits) {
410 assert(SU->isScheduled &&
411 SU->NumPredsLeft == 0);
419 for (SUnit* SU : SUnits) {
420 SU->isScheduled = false;
421 for (SDep& Succ : SU->Succs) {
423 undoReleaseSucc(SU, &Succ);
431 void SIScheduleBlock::undoReleaseSucc(SUnit *SU, SDep *SuccEdge) {
441 void SIScheduleBlock::releaseSucc(SUnit *SU, SDep *SuccEdge) {
460 /// Release Successors of the SU that are in the block or not.
461 void SIScheduleBlock::releaseSuccessors(SUnit *SU, bool InOrOutBlock) {
462 for (SDep& Succ : SU->Succs) {
471 releaseSucc(SU, &Succ);
477 void SIScheduleBlock::nodeScheduled(SUnit *SU) {
479 assert (!SU->NumPredsLeft);
480 std::vector<SUnit *>::iterator I = llvm::find(TopReadySUs, SU);
487 releaseSuccessors(SU, true);
490 if (HasLowLatencyNonWaitedParent[NodeNum2Index[SU->NodeNum]])
493 if (DAG->IsLowLatencySU[SU->NodeNum]) {
494 for (SDep& Succ : SU->Succs) {
501 SU->isScheduled = true;
506 for (SUnit* SU : SUnits) {
507 releaseSuccessors(SU, false);
508 if (DAG->IsHighLatencySU[SU->NodeNum])
592 for (const SUnit* SU : SUnits)
593 DAG->dumpNode(*SU);
623 bool SIScheduleBlockCreator::isSUInBlock(SUnit *SU, unsigned ID) {
624 if (SU->NodeNum >= DAG->SUnits.size())
626 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID;
633 SUnit *SU = &DAG->SUnits[i];
634 if (DAG->IsHighLatencySU[SU->NodeNum]) {
635 CurrentColoring[SU->NodeNum] = NextReservedID++;
641 hasDataDependencyPred(const SUnit &SU, const SUnit &FromSU) {
642 for (const auto &PredDep : SU.Preds) {
659 SUnit *SU = &DAG->SUnits[i];
660 if (DAG->IsHighLatencySU[SU->NodeNum])
675 const SUnit &SU = DAG->SUnits[SUNum];
676 if (DAG->IsHighLatencySU[SU.NodeNum]) {
694 // By construction (topological order), if SU and
696 // in the parent graph of SU.
698 SubGraph = DAG->GetTopo()->GetSubGraph(SU, DAG->SUnits[j],
702 SubGraph = DAG->GetTopo()->GetSubGraph(DAG->SUnits[j], SU,
722 // If one of the SU in the subgraph depends on the result of SU j,
731 // Same check for the SU
732 if (hasDataDependencyPred(SU, DAG->SUnits[j])) {
744 FormingGroup.insert(SU.NodeNum);
747 CurrentColoring[SU.NodeNum] = ProposedColor;
757 FormingGroup.insert(SU.NodeNum);
758 CurrentColoring[SU.NodeNum] = ProposedColor;
784 SUnit *SU = &DAG->SUnits[SUNum];
788 if (CurrentColoring[SU->NodeNum]) {
789 CurrentTopDownReservedDependencyColoring[SU->NodeNum] =
790 CurrentColoring[SU->NodeNum];
794 for (SDep& PredDep : SU->Preds) {
806 CurrentTopDownReservedDependencyColoring[SU->NodeNum] =
812 CurrentTopDownReservedDependencyColoring[SU->NodeNum] = Pos->second;
814 CurrentTopDownReservedDependencyColoring[SU->NodeNum] =
826 SUnit *SU = &DAG->SUnits[SUNum];
830 if (CurrentColoring[SU->NodeNum]) {
831 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] =
832 CurrentColoring[SU->NodeNum];
836 for (SDep& SuccDep : SU->Succs) {
848 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] =
854 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] = Pos->second;
856 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] =
870 for (const SUnit &SU : DAG->SUnits) {
874 if (CurrentColoring[SU.NodeNum])
877 SUColors.first = CurrentTopDownReservedDependencyColoring[SU.NodeNum];
878 SUColors.second = CurrentBottomUpReservedDependencyColoring[SU.NodeNum];
882 CurrentColoring[SU.NodeNum] = Pos->second;
902 SUnit *SU = &DAG->SUnits[SUNum];
906 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
909 if (CurrentBottomUpReservedDependencyColoring[SU->NodeNum] > 0 ||
910 CurrentTopDownReservedDependencyColoring[SU->NodeNum] > 0)
913 for (SDep& SuccDep : SU->Succs) {
926 PendingColoring[SU->NodeNum] = *SUColors.begin();
929 PendingColoring[SU->NodeNum] = NextNonReservedID++;
946 SUnit *SU = &DAG->SUnits[i];
949 assert(i == SU->NodeNum);
955 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
972 SUnit *SU = &DAG->SUnits[SUNum];
975 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
980 if (SU->Preds.size() > 0 && !DAG->IsLowLatencySU[SU->NodeNum])
983 for (SDep& SuccDep : SU->Succs) {
990 CurrentColoring[SU->NodeNum] = *SUColors.begin();
998 SUnit *SU = &DAG->SUnits[SUNum];
1001 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1004 for (SDep& SuccDep : SU->Succs) {
1011 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1019 SUnit *SU = &DAG->SUnits[SUNum];
1022 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1025 for (SDep& SuccDep : SU->Succs) {
1032 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1041 SUnit *SU = &DAG->SUnits[SUNum];
1042 unsigned color = CurrentColoring[SU->NodeNum];
1047 SUnit *SU = &DAG->SUnits[SUNum];
1048 unsigned color = CurrentColoring[SU->NodeNum];
1051 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1057 for (SDep& SuccDep : SU->Succs) {
1065 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1080 SUnit *SU = &DAG->SUnits[SUNum];
1083 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1086 for (SDep& SuccDep : SU->Succs) {
1093 CurrentColoring[SU->NodeNum] = GroupID;
1112 const SUnit &SU = DAG->SUnits[SUNum];
1113 if (SIInstrInfo::isEXP(*SU.getInstr())) {
1114 // SU is an export instruction. Check whether one of its successor
1116 for (const SDep &SuccDep : SU.Succs) {
1177 SUnit *SU = &DAG->SUnits[i];
1178 unsigned Color = CurrentColoring[SU->NodeNum];
1185 CurrentBlocks[RealID[Color]]->addUnit(SU);
1186 Node2CurrentBlock[SU->NodeNum] = RealID[Color];
1191 SUnit *SU = &DAG->SUnits[i];
1193 for (SDep& SuccDep : SU->Succs) {
1201 for (SDep& PredDep : SU->Preds) {
1309 for (SUnit* SU : SUs) {
1310 MachineInstr *MI = SU->getInstr();
1732 for (SUnit* SU : SUs)
1733 Res.SUs.push_back(SU->NodeNum);
1773 SUnit *SU = &SUnits[ScheduledSUnits[i]];
1777 for (SDep& PredDep : SU->Preds) {
1789 if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
1800 ScheduledSUnits[BestPos] = SU->NodeNum;
1801 ScheduledSUnitsInv[SU->NodeNum] = BestPos;
1810 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) {
1812 for (SDep& SuccDep : SU->Succs) {
1827 ScheduledSUnits[MinPos] = SU->NodeNum;
1828 ScheduledSUnitsInv[SU->NodeNum] = MinPos;
1901 SUnit *SU = &SUnits[i];
1904 if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
1907 if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
1910 } else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))
1976 SUnit *SU = &SUnits[I];
1978 scheduleMI(SU, true);
1980 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
1981 << *SU->getInstr());