Lines Matching defs:MI
54 void insert(MachineInstr *MI);
73 bool isDeferred(MachineInstr *MI);
109 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
116 MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
181 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
183 bool verifyCopy(const MachineInstr &MI, const MachineRegisterInfo &MRI,
191 isCopyInstrImpl(const MachineInstr &MI) const override;
193 bool swapSourceModifiers(MachineInstr &MI,
196 bool isLegalToSwap(const MachineInstr &MI, unsigned fromIdx,
199 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
237 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
241 bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
247 bool isGlobalMemoryObject(const MachineInstr *MI) const override;
265 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
271 MachineBasicBlock::iterator MI, const DebugLoc &DL,
286 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
292 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
297 bool expandPostRAPseudo(MachineInstr &MI) const override;
299 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
310 expandMovDPP64(MachineInstr &MI) const;
327 inline int commuteOpcode(const MachineInstr &MI) const {
328 return commuteOpcode(MI.getOpcode());
331 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
340 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
389 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
401 static bool isFoldableCopy(const MachineInstr &MI);
403 void removeModOperands(MachineInstr &MI) const;
410 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
413 bool isSchedulingBoundary(const MachineInstr &MI,
417 static bool isSALU(const MachineInstr &MI) {
418 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
425 static bool isVALU(const MachineInstr &MI) {
426 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
433 static bool isImage(const MachineInstr &MI) {
434 return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
441 static bool isVMEM(const MachineInstr &MI) {
442 return isMUBUF(MI) || isMTBUF(MI) || isImage(MI);
449 static bool isSOP1(const MachineInstr &MI) {
450 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
457 static bool isSOP2(const MachineInstr &MI) {
458 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
465 static bool isSOPC(const MachineInstr &MI) {
466 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
473 static bool isSOPK(const MachineInstr &MI) {
474 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
481 static bool isSOPP(const MachineInstr &MI) {
482 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
489 static bool isPacked(const MachineInstr &MI) {
490 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
497 static bool isVOP1(const MachineInstr &MI) {
498 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
505 static bool isVOP2(const MachineInstr &MI) {
506 return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
513 static bool isVOP3(const MachineInstr &MI) {
514 return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
521 static bool isSDWA(const MachineInstr &MI) {
522 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
529 static bool isVOPC(const MachineInstr &MI) {
530 return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
537 static bool isMUBUF(const MachineInstr &MI) {
538 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
545 static bool isMTBUF(const MachineInstr &MI) {
546 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
553 static bool isSMRD(const MachineInstr &MI) {
554 return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
561 bool isBufferSMRD(const MachineInstr &MI) const;
563 static bool isDS(const MachineInstr &MI) {
564 return MI.getDesc().TSFlags & SIInstrFlags::DS;
571 static bool isLDSDMA(const MachineInstr &MI) {
572 return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI));
579 static bool isGWS(const MachineInstr &MI) {
580 return MI.getDesc().TSFlags & SIInstrFlags::GWS;
589 static bool isMIMG(const MachineInstr &MI) {
590 return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
597 static bool isVIMAGE(const MachineInstr &MI) {
598 return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
605 static bool isVSAMPLE(const MachineInstr &MI) {
606 return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
613 static bool isGather4(const MachineInstr &MI) {
614 return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
621 static bool isFLAT(const MachineInstr &MI) {
622 return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
627 static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
628 auto Flags = MI.getDesc().TSFlags;
637 static bool isFLATGlobal(const MachineInstr &MI) {
638 return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
645 static bool isFLATScratch(const MachineInstr &MI) {
646 return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
658 static bool isEXP(const MachineInstr &MI) {
659 return MI.getDesc().TSFlags & SIInstrFlags::EXP;
662 static bool isDualSourceBlendEXP(const MachineInstr &MI) {
663 if (!isEXP(MI))
665 unsigned Target = MI.getOperand(0).getImm();
674 static bool isAtomicNoRet(const MachineInstr &MI) {
675 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
682 static bool isAtomicRet(const MachineInstr &MI) {
683 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
690 static bool isAtomic(const MachineInstr &MI) {
691 return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
700 static bool mayWriteLDSThroughDMA(const MachineInstr &MI) {
701 return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD;
704 static bool isWQM(const MachineInstr &MI) {
705 return MI.getDesc().TSFlags & SIInstrFlags::WQM;
712 static bool isDisableWQM(const MachineInstr &MI) {
713 return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
725 static bool isVGPRSpill(const MachineInstr &MI) {
726 return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
727 MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
728 (isSpill(MI) && isVALU(MI));
737 static bool isSGPRSpill(const MachineInstr &MI) {
738 return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
739 MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
740 (isSpill(MI) && isSALU(MI));
753 static bool isSpill(const MachineInstr &MI) {
754 return MI.getDesc().TSFlags & SIInstrFlags::Spill;
769 static bool isDPP(const MachineInstr &MI) {
770 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
777 static bool isTRANS(const MachineInstr &MI) {
778 return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
785 static bool isVOP3P(const MachineInstr &MI) {
786 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
793 static bool isVINTRP(const MachineInstr &MI) {
794 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
801 static bool isMAI(const MachineInstr &MI) {
802 return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
809 static bool isMFMA(const MachineInstr &MI) {
810 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
811 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
814 static bool isDOT(const MachineInstr &MI) {
815 return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
818 static bool isWMMA(const MachineInstr &MI) {
819 return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
826 static bool isMFMAorWMMA(const MachineInstr &MI) {
827 return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
830 static bool isSWMMAC(const MachineInstr &MI) {
831 return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
842 static bool isLDSDIR(const MachineInstr &MI) {
843 return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
850 static bool isVINTERP(const MachineInstr &MI) {
851 return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
858 static bool isScalarUnit(const MachineInstr &MI) {
859 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
862 static bool usesVM_CNT(const MachineInstr &MI) {
863 return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
866 static bool usesLGKM_CNT(const MachineInstr &MI) {
867 return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
881 static bool isScalarStore(const MachineInstr &MI) {
882 return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
889 static bool isFixedSize(const MachineInstr &MI) {
890 return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
897 static bool hasFPClamp(const MachineInstr &MI) {
898 return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
905 static bool hasIntClamp(const MachineInstr &MI) {
906 return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
909 uint64_t getClampMask(const MachineInstr &MI) const {
914 return MI.getDesc().TSFlags & ClampFlags;
917 static bool usesFPDPRounding(const MachineInstr &MI) {
918 return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
925 static bool isFPAtomic(const MachineInstr &MI) {
926 return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
933 static bool isNeverUniform(const MachineInstr &MI) {
934 return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
966 static bool doesNotReadTiedSource(const MachineInstr &MI) {
967 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
979 bool isIGLP(const MachineInstr &MI) const { return isIGLP(MI.getOpcode()); }
1027 bool isVGPRCopy(const MachineInstr &MI) const {
1028 assert(isCopyInstr(MI));
1029 Register Dest = MI.getOperand(0).getReg();
1030 const MachineFunction &MF = *MI.getParent()->getParent();
1035 bool hasVGPRUses(const MachineInstr &MI) const {
1036 const MachineFunction &MF = *MI.getParent()->getParent();
1038 return llvm::any_of(MI.explicit_uses(),
1044 static bool modifiesModeRegister(const MachineInstr &MI);
1053 bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
1057 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
1077 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
1079 bool isInlineConstant(const MachineInstr &MI,
1082 assert(UseMO.getParent() == &MI);
1084 if (OpIdx >= MI.getDesc().NumOperands)
1087 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
1090 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
1092 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
1093 const MachineOperand &MO = MI.getOperand(OpIdx);
1094 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1097 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
1099 if (OpIdx >= MI.getDesc().NumOperands)
1102 if (isCopyInstr(MI)) {
1103 unsigned Size = getOpSize(MI, OpIdx);
1111 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1118 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
1130 bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineInstr &MI,
1132 return usesConstantBus(MRI, MI.getOperand(OpIdx),
1133 MI.getDesc().operands()[OpIdx]);
1140 bool hasModifiersSet(const MachineInstr &MI,
1142 bool hasAnyModifiersSet(const MachineInstr &MI) const;
1144 bool canShrink(const MachineInstr &MI,
1147 MachineInstr *buildShrunkInst(MachineInstr &MI,
1150 bool verifyInstruction(const MachineInstr &MI,
1153 unsigned getVALUOp(const MachineInstr &MI) const;
1169 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1188 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
1189 const MachineOperand &MO = MI.getOperand(OpNo);
1195 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
1207 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
1210 /// for \p MI.
1211 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
1227 bool isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
1229 /// Legalize operands in \p MI by either commuting it or inserting a
1231 void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1233 /// Fix operands in \p MI to satisfy constant bus requirements.
1234 void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1245 void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1246 void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1255 /// instructions and control-flow around \p MI. If present, \p MDT is
1257 /// \returns A new basic block that contains \p MI if new blocks were created.
1259 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1275 MachineBasicBlock::iterator MI) const override;
1277 void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1287 MachineInstr &MI,
1292 static unsigned getNumWaitStates(const MachineInstr &MI);
1294 /// Returns the operand named \p Op. If \p MI does not have an
1297 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1300 const MachineOperand *getNamedOperand(const MachineInstr &MI,
1302 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1306 int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1307 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1308 return MI.getOperand(Idx).getImm();
1314 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1323 unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1324 unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1326 Register isLoadFromStackSlot(const MachineInstr &MI,
1328 Register isStoreToStackSlot(const MachineInstr &MI,
1331 unsigned getInstBundleSize(const MachineInstr &MI) const;
1332 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1334 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1362 bool isBasicBlockPrologue(const MachineInstr &MI,
1432 void fixImplicitOperands(MachineInstr &MI) const;
1434 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1442 const MachineInstr &MI,
1446 getInstructionUniformity(const MachineInstr &MI) const override final;
1449 getGenericInstructionUniformity(const MachineInstr &MI) const;
1464 void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1486 TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,