Lines Matching defs:SrcOp

2197     const MachineOperand &SrcOp = MI.getOperand(1);
2199     assert(!SrcOp.isFPImm());
2202       if (SrcOp.isReg() || isInlineConstant(MI, 1) ||
2203           isUInt<32>(SrcOp.getImm()))
2206     if (SrcOp.isImm()) {
2207       APInt Imm(64, SrcOp.getImm());
2230       assert(SrcOp.isReg());
2232           !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) {
2235           .addReg(SrcOp.getReg())
2237           .addReg(SrcOp.getReg())
2245           .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
2248           .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
2260     const MachineOperand &SrcOp = MI.getOperand(1);
2261     assert(!SrcOp.isFPImm());
2262     APInt Imm(64, SrcOp.getImm());
2662       const MachineOperand &SrcOp = MI.getOperand(I);
2663       assert(!SrcOp.isFPImm());
2664       if (SrcOp.isImm()) {
2665         APInt Imm(64, SrcOp.getImm());
2669         assert(SrcOp.isReg());
2670         Register Src = SrcOp.getReg();
2674           MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
5451     const MachineOperand &SrcOp = MI.getOperand(1);
5452     if (!SrcOp.isReg() || SrcOp.getReg().isVirtual()) {
9854     const MachineOperand &SrcOp = MI.getOperand(I);
9855     if (!SrcOp.isReg())
9858     Register Reg = SrcOp.getReg();
9859     if (!Reg || !SrcOp.readsReg())
10014     MachineOperand *SrcOp = &Def->getOperand(1);
10015     if (isMask(SrcOp))
10016       SrcOp = &Def->getOperand(2);
10018       SrcOp = &Def->getOperand(1);
10070       .add(*SrcOp)