Lines Matching defs:Src0RC

6855     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
6856     if (DstRC != Src0RC) {
8020   const TargetRegisterClass *Src0RC = Src0.isReg() ?
8025       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);
8027   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8038   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8084   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
8087       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);
8098       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8102       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
8193   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
8196       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);
8207       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
8254   const TargetRegisterClass *Src0RC = Src0.isReg() ?
8259       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);
8267   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
8271   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,