Lines Matching defs:SIInstrInfo
1 //===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
14 #include "SIInstrInfo.h"
63 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
109 if (SIInstrInfo::isVOP1(MI) || SIInstrInfo::isVOP2(MI) ||
110 SIInstrInfo::isVOP3(MI) || SIInstrInfo::isSDWA(MI) ||
111 SIInstrInfo::isSALU(MI))
114 if (SIInstrInfo::isSMRD(MI)) {
124 bool SIInstrInfo::isReallyTriviallyReMaterializable(
184 bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {
190 bool SIInstrInfo::isSafeToSink(MachineInstr &MI,
230 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
356 bool SIInstrInfo::getMemOperandsWithOffsetWidth(
549 bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
601 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
613 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,
630 static void indirectCopyToAGPR(const SIInstrInfo &TII,
749 static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
801 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1155 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
1173 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,
1230 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {
1234 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
1258 case SIInstrInfo::SCC_TRUE: {
1272 case SIInstrInfo::SCC_FALSE: {
1286 case SIInstrInfo::VCCNZ: {
1300 case SIInstrInfo::VCCZ: {
1314 case SIInstrInfo::EXECNZ: {
1332 case SIInstrInfo::EXECZ: {
1359 Register SIInstrInfo::insertEQ(MachineBasicBlock *MBB,
1372 Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,
1385 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
1404 SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,
1537 SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,
1724 void SIInstrInfo::storeRegToStackSlot(
1950 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2003 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,
2008 void SIInstrInfo::insertNoops(MachineBasicBlock &MBB,
2019 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {
2037 MachineBasicBlock *SIInstrInfo::insertSimulatedTrap(MachineRegisterInfo &MRI,
2095 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {
2109 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
2546 void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,
2633 SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {
2697 SIInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
2704 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,
2767 bool SIInstrInfo::isLegalToSwap(const MachineInstr &MI, unsigned OpIdx0,
2811 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2867 bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2873 bool SIInstrInfo::findCommutedOpIndices(const MCInstrDesc &Desc,
2891 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
2908 SIInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
2912 bool SIInstrInfo::hasDivergentBranch(const MachineBasicBlock *MBB) const {
2921 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
3051 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
3053 case SIInstrInfo::SCC_TRUE:
3055 case SIInstrInfo::SCC_FALSE:
3057 case SIInstrInfo::VCCNZ:
3059 case SIInstrInfo::VCCZ:
3061 case SIInstrInfo::EXECNZ:
3063 case SIInstrInfo::EXECZ:
3070 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
3089 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,
3126 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
3171 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,
3197 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
3249 bool SIInstrInfo::reverseBranchCondition(
3263 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3305 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
3412 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {
3440 void SIInstrInfo::removeModOperands(MachineInstr &MI) const {
3449 bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
3743 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
3767 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
3836 if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {
3896 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
3935 if (SIInstrInfo::isWMMA(MI)) {
4169 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
4200 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
4204 bool SIInstrInfo::modifiesModeRegister(const MachineInstr &MI) {
4211 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {
4257 bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,
4282 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
4302 bool SIInstrInfo::isInlineConstant(const APFloat &Imm) const {
4321 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
4447 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
4477 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
4489 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
4496 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
4502 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {
4507 bool SIInstrInfo::canShrink(const MachineInstr &MI,
4582 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
4627 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
4676 if (SIInstrInfo::isVALU(MI)) {
4689 SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
4690 SIInstrInfo::isSALU(MI) ||
4691 SIInstrInfo::isSMRD(MI))
4712 bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
4725 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
4740 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
5464 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
5661 void SIInstrInfo::insertScratchExecCopy(MachineFunction &MF,
5668 const SIInstrInfo *TII = ST.getInstrInfo();
5694 void SIInstrInfo::restoreExec(MachineFunction &MF, MachineBasicBlock &MBB,
5742 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
5772 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
5789 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
5812 unsigned SIInstrInfo::buildExtractSubReg(
5829 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
5848 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
5855 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
5882 bool SIInstrInfo::isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
5925 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
5936 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
6022 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
6140 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
6231 Register SIInstrInfo::readlaneVGPRToSGPR(
6277 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
6296 bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
6377 void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,
6398 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
6443 emitLoadScalarOpsFromVGPRLoop(const SIInstrInfo &TII,
6587 loadMBUFScalarOperandsFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,
6694 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
6736 SIInstrInfo::legalizeOperands(MachineInstr &MI,
7132 void SIInstrInfo::moveToVALU(SIInstrWorklist &Worklist,
7153 void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
7740 SIInstrInfo::moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
7775 void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
7857 void SIInstrInfo::lowerScalarAbs(SIInstrWorklist &Worklist,
7884 void SIInstrInfo::lowerScalarXnor(SIInstrWorklist &Worklist,
7949 void SIInstrInfo::splitScalarNotBinop(SIInstrWorklist &Worklist,
7978 void SIInstrInfo::splitScalarBinOpN2(SIInstrWorklist &Worklist,
8007 void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist,
8068 void SIInstrInfo::splitScalarSMulU64(SIInstrWorklist &Worklist,
8177 void SIInstrInfo::splitScalarSMulPseudo(SIInstrWorklist &Worklist,
8240 void SIInstrInfo::splitScalar64BitBinaryOp(SIInstrWorklist &Worklist,
8307 void SIInstrInfo::splitScalar64BitXnor(SIInstrWorklist &Worklist,
8349 void SIInstrInfo::splitScalar64BitBCNT(SIInstrWorklist &Worklist,
8387 void SIInstrInfo::splitScalar64BitBFE(SIInstrWorklist &Worklist,
8448 void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,
8503 void SIInstrInfo::addUsersToMoveToVALUWorklist(
8539 void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist,
8612 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
8656 void SIInstrInfo::addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
8674 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
8724 Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
8794 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
8803 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
8828 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
8852 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {
8858 bool SIInstrInfo::isHighLatencyDef(int Opc) const {
8863 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
8876 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
8884 Register SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
8898 Register SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
8912 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {
8924 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
8985 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {
9000 SIInstrInfo::getSerializableTargetIndices() const {
9013 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
9021 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
9028 SIInstrInfo::CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
9040 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
9045 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
9060 SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const {
9070 unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
9080 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
9106 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
9121 MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
9144 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {
9154 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {
9165 bool SIInstrInfo::isLegalMUBUFImmOffset(unsigned Imm) const {
9169 unsigned SIInstrInfo::getMaxMUBUFImmOffset(const GCNSubtarget &ST) {
9176 void SIInstrInfo::fixImplicitOperands(MachineInstr &MI) const {
9189 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {
9209 bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset,
9211 const uint32_t MaxOffset = SIInstrInfo::getMaxMUBUFImmOffset(ST);
9285 bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
9307 // See comment on SIInstrInfo::isLegalFLATOffset for what is legal and what not.
9309 SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,
9340 bool SIInstrInfo::allowNegativeFlatOffset(uint64_t FlatVariant) const {
9368 bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {
9421 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
9422 Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);
9653 MachineInstr *SIInstrInfo::createPHIDestinationCopy(
9668 MachineInstr *SIInstrInfo::createPHISourceCopy(
9688 bool llvm::SIInstrInfo::isWave32() const { return ST.isWave32(); }
9690 MachineInstr *SIInstrInfo::foldMemoryOperandImpl(
9728 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
9746 SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
9785 if (SIInstrInfo::isGenericAtomicRMWOpcode(opcode) ||
9795 SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {
9819 return SIInstrInfo::getGenericInstructionUniformity(MI);
9879 unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {
9901 bool SIInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
9960 bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
10111 void SIInstrInfo::enforceOperandRCAlignment(MachineInstr &MI,
10145 bool SIInstrInfo::isGlobalMemoryObject(const MachineInstr *MI) const {