Lines Matching defs:InstDesc

2770   const MCInstrDesc &InstDesc = MI.getDesc();
2771   const MCOperandInfo &OpInfo0 = InstDesc.operands()[OpIdx0];
2772   const MCOperandInfo &OpInfo1 = InstDesc.operands()[OpIdx1];
4449   const MCInstrDesc &InstDesc = MI.getDesc();
4450   const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];
4471   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
5940   const MCInstrDesc &InstDesc = MI.getDesc();
5941   const MCOperandInfo &OpInfo = InstDesc.operands()[OpIdx];
5965             usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) {
5970       } else if (AMDGPU::isSISrcOperand(InstDesc, i) &&
5971                  !isInlineConstant(Op, InstDesc.operands()[i])) {
8019   const MCInstrDesc &InstDesc = get(Opcode);
8036   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
8042   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
8253   const MCInstrDesc &InstDesc = get(Opcode);
8282   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
8287   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
8360   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
8376   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
8378   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
8464   const MCInstrDesc &InstDesc = get(Opcode);
8485   BuildMI(MBB, MII, DL, InstDesc, MidReg1).add(SrcRegSub0);
8487   BuildMI(MBB, MII, DL, InstDesc, MidReg2).add(SrcRegSub1);