Lines Matching defs:ScoreBrackets
488 applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
529 applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
565 applyPreexistingWaitcnt(WaitcntBrackets &ScoreBrackets,
641 WaitcntBrackets &ScoreBrackets);
727 WaitcntBrackets &ScoreBrackets,
732 MachineBasicBlock &Block, WaitcntBrackets &ScoreBrackets,
735 WaitcntBrackets *ScoreBrackets);
737 WaitcntBrackets &ScoreBrackets);
1189 WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr,
1212 ScoreBrackets.simplifyWaitcnt(OldWait);
1228 ScoreBrackets.simplifyWaitcnt(InstCounterType::STORE_CNT, OldVSCnt);
1244 ScoreBrackets.applyWaitcnt(LOAD_CNT, Wait.LoadCnt);
1245 ScoreBrackets.applyWaitcnt(EXP_CNT, Wait.ExpCnt);
1246 ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt);
1265 ScoreBrackets.applyWaitcnt(STORE_CNT, Wait.StoreCnt);
1336 WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr,
1369 ScoreBrackets.simplifyWaitcnt(OldWait);
1377 ScoreBrackets.simplifyWaitcnt(OldWait);
1386 ScoreBrackets.simplifyWaitcnt(CT.value(), OldCnt);
1413 ScoreBrackets.applyWaitcnt(LOAD_CNT, Wait.LoadCnt);
1414 ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt);
1438 ScoreBrackets.applyWaitcnt(STORE_CNT, Wait.StoreCnt);
1439 ScoreBrackets.applyWaitcnt(DS_CNT, Wait.DsCnt);
1499 ScoreBrackets.applyWaitcnt(CT, NewCnt);
1614 WaitcntBrackets &ScoreBrackets,
1654 ScoreBrackets.getScoreRange(STORE_CNT) != 0 &&
1655 !ScoreBrackets.hasPendingEvent(SCRATCH_WRITE_ACCESS))
1675 if (ScoreBrackets.hasPendingEvent(EXP_GPR_LOCK) ||
1676 ScoreBrackets.hasPendingEvent(EXP_PARAM_ACCESS) ||
1677 ScoreBrackets.hasPendingEvent(EXP_POS_ACCESS) ||
1678 ScoreBrackets.hasPendingEvent(GDS_GPR_LOCK)) {
1692 ScoreBrackets.getRegInterval(&MI, MRI, TRI, CallAddrOp);
1694 ScoreBrackets.determineWait(SmemAccessCounter, CallAddrOpInterval,
1700 ScoreBrackets.getRegInterval(&MI, MRI, TRI, *RtnAddrOp);
1702 ScoreBrackets.determineWait(SmemAccessCounter, RtnAddrOpInterval,
1745 const auto &LDSDMAStores = ScoreBrackets.getLDSDMAStores();
1749 ScoreBrackets.determineWait(LOAD_CNT, RegNo + I + 1, Wait);
1754 ScoreBrackets.determineWait(LOAD_CNT, RegNo, Wait);
1756 ScoreBrackets.determineWait(EXP_CNT, RegNo, Wait);
1769 RegInterval Interval = ScoreBrackets.getRegInterval(&MI, MRI, TRI, Op);
1786 ScoreBrackets.hasOtherPendingVmemTypes(Interval,
1789 ScoreBrackets.determineWait(LOAD_CNT, Interval, Wait);
1790 ScoreBrackets.determineWait(SAMPLE_CNT, Interval, Wait);
1791 ScoreBrackets.determineWait(BVH_CNT, Interval, Wait);
1792 ScoreBrackets.clearVgprVmemTypes(Interval);
1794 if (Op.isDef() || ScoreBrackets.hasPendingEvent(EXP_LDS_ACCESS)) {
1795 ScoreBrackets.determineWait(EXP_CNT, Interval, Wait);
1797 ScoreBrackets.determineWait(DS_CNT, Interval, Wait);
1799 ScoreBrackets.determineWait(SmemAccessCounter, Interval, Wait);
1818 if (ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) {
1824 ScoreBrackets.simplifyWaitcnt(Wait);
1845 if (ScoreBrackets.hasPendingEvent(LOAD_CNT))
1847 if (ScoreBrackets.hasPendingEvent(SAMPLE_CNT))
1849 if (ScoreBrackets.hasPendingEvent(BVH_CNT))
1853 return generateWaitcnt(Wait, MI.getIterator(), *MI.getParent(), ScoreBrackets,
1860 WaitcntBrackets &ScoreBrackets,
1868 WCG->applyPreexistingWaitcnt(ScoreBrackets, *OldWaitcntInstr, Wait, It);
1872 ScoreBrackets.applyWaitcnt(Wait);
1985 WaitcntBrackets *ScoreBrackets) {
1994 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_ACCESS, Inst);
1995 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_GPR_LOCK, Inst);
1997 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst);
2010 ScoreBrackets->updateByEvent(TII, TRI, MRI, getVmemWaitEventType(Inst),
2016 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst);
2026 ScoreBrackets->setPendingFlat();
2029 ScoreBrackets->updateByEvent(TII, TRI, MRI, getVmemWaitEventType(Inst),
2034 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMW_GPR_LOCK, Inst);
2037 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
2041 ScoreBrackets->applyWaitcnt(
2043 ScoreBrackets->setStateOnFunctionEntryOrReturn();
2046 ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt());
2049 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_LDS_ACCESS, Inst);
2052 ScoreBrackets->applyWaitcnt(EXP_CNT, Imm);
2056 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_PARAM_ACCESS, Inst);
2058 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_POS_ACCESS, Inst);
2060 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_GPR_LOCK, Inst);
2067 ScoreBrackets->updateByEvent(TII, TRI, MRI, SQ_MESSAGE, Inst);
2076 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
2158 WaitcntBrackets &ScoreBrackets) {
2163 ScoreBrackets.dump();
2198 isPreheaderToFlush(Block, ScoreBrackets);
2201 Modified |= generateWaitcntInstBefore(Inst, ScoreBrackets, OldWaitcntInstr,
2224 ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) {
2250 updateEventWaitcntAfter(Inst, &ScoreBrackets);
2255 ScoreBrackets.simplifyWaitcnt(Wait);
2257 ScoreBrackets, /*OldWaitcntInstr=*/nullptr);
2262 ScoreBrackets.dump();
2286 isPreheaderToFlush(Block, ScoreBrackets)) {
2287 if (ScoreBrackets.hasPendingEvent(LOAD_CNT))
2289 if (ScoreBrackets.hasPendingEvent(SAMPLE_CNT))
2291 if (ScoreBrackets.hasPendingEvent(BVH_CNT))
2296 Modified |= generateWaitcnt(Wait, Block.instr_end(), Block, ScoreBrackets,
2305 WaitcntBrackets &ScoreBrackets) {
2319 shouldFlushVmCnt(Loop, ScoreBrackets)) {