Lines Matching defs:MaxCounter

83 // and \c MaxCounter (exclusive, default value yields an enumeration over
85 auto inst_counter_types(InstCounterType MaxCounter = NUM_INST_CNTS) {
86   return enum_seq(LOAD_CNT, MaxCounter);
177 static bool isNormalMode(InstCounterType MaxCounter) {
178   return MaxCounter == NUM_NORMAL_INST_CNTS;
251   WaitcntBrackets(const GCNSubtarget *SubTarget, InstCounterType MaxCounter,
255       : ST(SubTarget), MaxCounter(MaxCounter), Limits(Limits),
424   InstCounterType MaxCounter = NUM_EXTENDED_INST_CNTS;
461   InstCounterType MaxCounter;
466   WaitcntGenerator(const MachineFunction &MF, InstCounterType MaxCounter)
468         IV(AMDGPU::getIsaVersion(ST->getCPU())), MaxCounter(MaxCounter),
561                             InstCounterType MaxCounter)
562       : WaitcntGenerator(MF, MaxCounter) {}
628   InstCounterType MaxCounter = NUM_NORMAL_INST_CNTS;
972   for (auto T : inst_counter_types(MaxCounter)) {
1192   assert(isNormalMode(MaxCounter));
1286   assert(isNormalMode(MaxCounter));
1339   assert(!isNormalMode(MaxCounter));
1523   assert(!isNormalMode(MaxCounter));
2102   for (auto T : inst_counter_types(MaxCounter)) {
2415     MaxCounter = NUM_EXTENDED_INST_CNTS;
2416     WCGGFX12Plus = WaitcntGeneratorGFX12Plus(MF, MaxCounter);
2419     MaxCounter = NUM_NORMAL_INST_CNTS;
2491         ST, MaxCounter, Limits, Encoding, WaitEventMaskForInst,
2524               ST, MaxCounter, Limits, Encoding, WaitEventMaskForInst,
2527           *Brackets = WaitcntBrackets(ST, MaxCounter, Limits, Encoding,