Lines Matching defs:getSubtarget
997 const GCNSubtarget *SITargetLowering::getSubtarget() const { return Subtarget; }
1723 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
2495 if (UserSGPRInfo.hasFlatScratchInit() && !getSubtarget()->isAmdPalOS()) {
2691 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
2783 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2819 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
3113 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
3566 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
4436 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4487 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4507 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4559 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4652 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5067 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
5073 return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MIN_U32);
5075 return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_U32);
5104 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5155 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5239 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5336 assert(MF->getSubtarget<GCNSubtarget>().hasShaderCyclesHiLoRegisters());
5385 return emitIndirectSrc(MI, *BB, *getSubtarget());
5396 return emitIndirectDst(MI, *BB, *getSubtarget());
5402 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5461 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
5478 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
5508 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
5537 if (getSubtarget()->hasGWSAutoReplay()) {
5561 if (getSubtarget()->hasDenormModeInst()) {
6167 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
6197 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
6254 const GCNSubtarget *ST = TLI.getSubtarget();
6787 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
8134 const GCNSubtarget *ST = &MF.getSubtarget<GCNSubtarget>();
8651 if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction()))
8799 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
9772 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
10323 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
11731 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
11853 if (getSubtarget()->hasSDWA() && LHS->getOpcode() == ISD::SRL &&
11964 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
12645 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
13454 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
13684 EltSize, NumElem, Idx->isDivergent(), getSubtarget());
14854 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15193 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15540 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15616 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15713 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
15804 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
16197 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
16272 DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
16296 Known.Zero.setHighBits(getSubtarget()->getKnownHighZeroBitsForFrameIndex());
16316 knownBitsForWorkitemID(*getSubtarget(), KB, Known, 0);
16319 knownBitsForWorkitemID(*getSubtarget(), KB, Known, 1);
16322 knownBitsForWorkitemID(*getSubtarget(), KB, Known, 2);
16329 ? getSubtarget()->getWavefrontSizeLog2()
16342 llvm::countl_zero(getSubtarget()->getAddressableLocalMemorySize()));
16402 if (!ML || DisableLoopAlignment || !getSubtarget()->hasInstPrefetch() ||
16403 getSubtarget()->hasInstFwdPrefetchBug())
16416 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();