Lines Matching defs:DCI
6908 DAGCombinerInfo &DCI) const {
6920 if (DCI.isBeforeLegalizeOps() ||
6924 auto &DAG = DCI.DAG;
7497 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
7503 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
10482 DAGCombinerInfo &DCI) const {
10483 SelectionDAG &DAG = DCI.DAG;
10498 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) ||
10536 DCI.AddToWorklist(Cvt.getNode());
10541 DCI.AddToWorklist(Cvt.getNode());
11534 DAGCombinerInfo &DCI) const {
11540 SelectionDAG &DAG = DCI.DAG;
11550 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) {
11553 DCI.AddToWorklist(Cvt.getNode());
11568 DAGCombinerInfo &DCI) const {
11571 SelectionDAG &DAG = DCI.DAG;
11628 DAGCombinerInfo &DCI) const {
11646 SelectionDAG &DAG = DCI.DAG;
11655 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext());
11660 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace))
11692 DAGCombinerInfo &DCI) const {
11693 SelectionDAG &DAG = DCI.DAG;
11702 N->getMemoryVT(), DCI);
11726 DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS,
11739 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi);
11830 DAGCombinerInfo &DCI) const {
11831 if (DCI.isBeforeLegalize())
11834 SelectionDAG &DAG = DCI.DAG;
11842 splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
12506 static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
12507 SelectionDAG &DAG = DCI.DAG;
12598 DAGCombinerInfo &DCI) const {
12599 SelectionDAG &DAG = DCI.DAG;
12711 if (SDValue Perm = matchPERM(N, DCI))
12716 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
12736 DCI.AddToWorklist(LowOr.getNode());
12737 DCI.AddToWorklist(HiBits.getNode());
12747 if (SDValue Split = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR,
12756 DAGCombinerInfo &DCI) const {
12757 if (SDValue RV = reassociateScalarOps(N, DCI.DAG))
12764 SelectionDAG &DAG = DCI.DAG;
12769 splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
12798 DAGCombinerInfo &DCI) const {
12800 DCI.getDAGCombineLevel() < AfterLegalizeDAG)
12816 DAGCombinerInfo &DCI) const {
12834 SDVTList ResList = DCI.DAG.getVTList(MVT::i32);
12841 SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode(
12843 SDValue LoadVal = DCI.DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad);
12861 DCI.DAG.getVTList(MVT::i32, Src.getOperand(0).getValueType());
12865 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(
12867 return DCI.DAG.getMergeValues(
12874 DAGCombinerInfo &DCI) const {
12875 SelectionDAG &DAG = DCI.DAG;
12889 DAGCombinerInfo &DCI) const {
12894 return DCI.DAG.getConstantFP(APFloat::getQNaN(VT.getFltSemantics()),
12900 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0,
12907 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT, N0.getOperand(0),
12911 return AMDGPUTargetLowering::performRcpCombine(N, DCI);
13273 DAGCombinerInfo &DCI) const {
13274 SelectionDAG &DAG = DCI.DAG;
13495 DAGCombinerInfo &DCI) const {
13496 SelectionDAG &DAG = DCI.DAG;
13579 DAGCombinerInfo &DCI) const {
13584 SelectionDAG &DAG = DCI.DAG;
13623 DAGCombinerInfo &DCI) const {
13627 return DCI.DAG.getUNDEF(N->getValueType(0));
13689 DAGCombinerInfo &DCI) const {
13691 SelectionDAG &DAG = DCI.DAG;
13714 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) {
13742 DCI.AddToWorklist(Elt0.getNode());
13743 DCI.AddToWorklist(Elt1.getNode());
13765 if (!DCI.isBeforeLegalize())
13782 DCI.AddToWorklist(Cast.getNode());
13786 DCI.AddToWorklist(Elt.getNode());
13789 DCI.AddToWorklist(Srl.getNode());
13793 DCI.AddToWorklist(Trunc.getNode());
13808 DAGCombinerInfo &DCI) const {
13819 SelectionDAG &DAG = DCI.DAG;
13855 DAGCombinerInfo &DCI) const {
13868 SelectionDAG &DAG = DCI.DAG;
14009 DAGCombinerInfo &DCI) const {
14012 SelectionDAG &DAG = DCI.DAG;
14130 DAGCombinerInfo &DCI) const {
14140 SelectionDAG &DAG = DCI.DAG;
14423 DAGCombinerInfo &DCI) const {
14424 SelectionDAG &DAG = DCI.DAG;
14432 if (SDValue Folded = tryFoldToMad64_32(N, DCI))
14442 if (SDValue Folded = foldAddSub64WithZeroLowBitsTo32(N, DCI))
14588 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
14627 DAGCombinerInfo &DCI) const {
14628 SelectionDAG &DAG = DCI.DAG;
14632 if (SDValue Folded = foldAddSub64WithZeroLowBitsTo32(N, DCI))
14676 DAGCombinerInfo &DCI) const {
14684 SelectionDAG &DAG = DCI.DAG;
14700 DAGCombinerInfo &DCI) const {
14701 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
14704 SelectionDAG &DAG = DCI.DAG;
14742 DAGCombinerInfo &DCI) const {
14743 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
14746 SelectionDAG &DAG = DCI.DAG;
14789 DAGCombinerInfo &DCI) const {
14790 SelectionDAG &DAG = DCI.DAG;
14824 DAGCombinerInfo &DCI) const {
14825 SelectionDAG &DAG = DCI.DAG;
14884 DAGCombinerInfo &DCI) const {
14885 SelectionDAG &DAG = DCI.DAG;
14957 DAGCombinerInfo &DCI) const {
14958 SelectionDAG &DAG = DCI.DAG;
15053 DAGCombinerInfo &DCI) const {
15054 SelectionDAG &DAG = DCI.DAG;
15090 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) {
15094 DCI.AddToWorklist(N);
15107 DAGCombinerInfo &DCI) const {
15112 const MachineFunction &MF = DCI.DAG.getMachineFunction();
15117 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0));
15122 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0));
15128 DAGCombinerInfo &DCI) const {
15145 if (auto Res = promoteUniformOpToI32(SDValue(N, 0), DCI))
15157 return performAddCombine(N, DCI);
15159 return performSubCombine(N, DCI);
15162 return performAddCarrySubCarryCombine(N, DCI);
15164 return performFAddCombine(N, DCI);
15166 return performFSubCombine(N, DCI);
15168 return performFDivCombine(N, DCI);
15170 return performFMulCombine(N, DCI);
15172 return performSetCCCombine(N, DCI);
15185 return performMinMaxCombine(N, DCI);
15187 return performFMACombine(N, DCI);
15189 return performAndCombine(N, DCI);
15191 return performOrCombine(N, DCI);
15196 return matchPERM(N, DCI);
15201 return performXorCombine(N, DCI);
15203 return performZeroExtendCombine(N, DCI);
15205 return performSignExtendInRegCombine(N, DCI);
15207 return performClassCombine(N, DCI);
15209 return performFCanonicalizeCombine(N, DCI);
15211 return performRcpCombine(N, DCI);
15226 return performUCharToFloatCombine(N, DCI);
15228 return performFCopySignCombine(N, DCI);
15233 return performCvtF32UByteNCombine(N, DCI);
15235 return performFMed3Combine(N, DCI);
15237 return performCvtPkRTZCombine(N, DCI);
15239 return performClampCombine(N, DCI);
15241 SelectionDAG &DAG = DCI.DAG;
15259 return performExtractVectorEltCombine(N, DCI);
15261 return performInsertVectorEltCombine(N, DCI);
15263 return performFPRoundCombine(N, DCI);
15265 if (SDValue Widened = widenLoad(cast<LoadSDNode>(N), DCI))
15270 if (!DCI.isBeforeLegalize()) {
15272 return performMemSDNodeCombine(MemNode, DCI);
15279 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);