Lines Matching defs:CCInfo
74 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
77 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
2260 CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI,
2269 CCInfo.AllocateReg(Reg);
2284 CCInfo.AllocateReg(Reg);
2298 CCInfo.AllocateReg(Reg);
2308 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
2314 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
2317 int64_t Offset = CCInfo.AllocateStack(4, Align(4));
2323 Reg = CCInfo.AllocateReg(Reg);
2326 MachineFunction &MF = CCInfo.getMachineFunction();
2332 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
2336 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
2341 Reg = CCInfo.AllocateReg(Reg);
2344 MachineFunction &MF = CCInfo.getMachineFunction();
2350 // CCInfo state. Technically we could get away with this for values passed
2352 static void allocateFixedSGPRInputImpl(CCState &CCInfo,
2355 Reg = CCInfo.AllocateReg(Reg);
2357 MachineFunction &MF = CCInfo.getMachineFunction();
2361 static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg) {
2363 allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_32RegClass,
2366 Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
2369 static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {
2371 allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_64RegClass,
2374 Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
2380 CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI,
2386 Arg = allocateVGPR32Input(CCInfo, Mask);
2391 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
2396 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
2401 CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI,
2403 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
2414 CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI,
2421 allocateSGPR64Input(CCInfo, ArgInfo.DispatchPtr);
2424 allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);
2429 allocateSGPR64Input(CCInfo, ArgInfo.ImplicitArgPtr);
2432 allocateSGPR64Input(CCInfo, ArgInfo.DispatchID);
2437 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDX);
2440 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDY);
2443 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDZ);
2446 allocateSGPR32Input(CCInfo, ArgInfo.LDSKernelId);
2450 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
2458 CCInfo.AllocateReg(ImplicitBufferPtrReg);
2465 CCInfo.AllocateReg(PrivateSegmentBufferReg);
2471 CCInfo.AllocateReg(DispatchPtrReg);
2477 CCInfo.AllocateReg(QueuePtrReg);
2483 CCInfo.AllocateReg(InputPtrReg);
2492 CCInfo.AllocateReg(DispatchIDReg);
2498 CCInfo.AllocateReg(FlatScratchInitReg);
2504 CCInfo.AllocateReg(PrivateSegmentSizeReg);
2514 CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,
2585 CCInfo.AllocateReg(Reg);
2593 void SITargetLowering::allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
2600 CCInfo.AllocateReg(Reg);
2605 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF,
2628 CCInfo.AllocateReg(Reg);
2636 CCInfo.AllocateReg(Reg);
2642 CCInfo.AllocateReg(Reg);
2648 CCInfo.AllocateReg(Reg);
2655 CCInfo.AllocateReg(Reg);
2669 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
2676 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
2836 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2877 CCInfo.AllocateReg(AMDGPU::VGPR0);
2878 CCInfo.AllocateReg(AMDGPU::VGPR1);
2903 analyzeFormalArgumentsCompute(CCInfo, Ins);
2906 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2907 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2909 allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, Ins, MF, *TRI, *Info);
2911 allocateLDSKernelId(CCInfo, MF, *TRI, *Info);
2914 allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
2918 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2920 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2925 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
3148 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
3157 unsigned StackArgSize = CCInfo.getStackSize();
3177 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3178 if (!CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)))
3185 if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))
3215 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3219 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
3295 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3297 CCInfo.AnalyzeCallResult(Ins, RetCC);
3345 CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info,
3429 if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
3433 CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));
3521 CCInfo.AllocateReg(OutgoingArg->getRegister());
3523 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));
3611 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
3615 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
3621 if (CCInfo.getStackSize() > FuncInfo->getBytesInStackArgArea())
3745 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3750 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
3753 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
3756 unsigned NumBytes = CCInfo.getStackSize();