Lines Matching defs:SuperReg

233   Register SuperReg;
255                             ? SuperReg
256                             : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
276                             ? SuperReg
277                             : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
288         .addReg(SuperReg)
303                             ? SuperReg
304                             : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
322                             ? SuperReg
323                             : Register(TRI.getSubReg(SuperReg, SplitParts[I]));
331     BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), SuperReg)
347         SuperReg(Reg), SI(SI), LiveUnits(LiveUnits), DL(DL),
349     const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg);
353     assert(SuperReg != AMDGPU::M0 && "m0 should never spill");