Lines Matching defs:LiveUnits
29 // Find a register matching \p RC from \p LiveUnits which is unused and
35 const LiveRegUnits &LiveUnits,
38 if (!MRI.isPhysRegUsed(Reg) && LiveUnits.available(Reg) &&
50 MachineRegisterInfo &MRI, LiveRegUnits &LiveUnits,
55 LiveUnits.addReg(CSRegs[i]);
60 return findUnusedRegister(MRI, LiveUnits, RC);
63 if (LiveUnits.available(Reg) && !MRI.isReserved(Reg))
73 MachineFunction &MF, LiveRegUnits &LiveUnits, Register SGPR,
88 // LiveUnits should have all the callee saved registers marked as used. For
91 ScratchSGPR = findUnusedRegister(MF.getRegInfo(), LiveUnits, RC);
125 LiveUnits.addReg(ScratchSGPR);
136 LiveRegUnits &LiveUnits, MachineFunction &MF,
149 LiveUnits.addReg(SpillReg);
152 DwordOff, MMO, nullptr, &LiveUnits);
154 LiveUnits.removeReg(SpillReg);
160 LiveRegUnits &LiveUnits, MachineFunction &MF,
174 DwordOff, MMO, nullptr, &LiveUnits);
202 static void initLiveUnits(LiveRegUnits &LiveUnits, const SIRegisterInfo &TRI,
206 if (LiveUnits.empty()) {
207 LiveUnits.init(TRI);
209 LiveUnits.addLiveIns(MBB);
212 LiveUnits.addLiveOuts(MBB);
213 LiveUnits.stepBackward(*MBBI);
235 LiveRegUnits &LiveUnits;
246 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ true);
249 MRI, LiveUnits, AMDGPU::VGPR_32RegClass);
260 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, TmpVGPR,
295 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MI, /*IsProlog*/ false);
297 MRI, LiveUnits, AMDGPU::VGPR_32RegClass);
306 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL,
343 LiveRegUnits &LiveUnits, Register FrameReg)
347 SuperReg(Reg), SI(SI), LiveUnits(LiveUnits), DL(DL),
405 LiveRegUnits LiveUnits;
406 LiveUnits.init(*TRI);
407 LiveUnits.addLiveIns(MBB);
418 if (LiveUnits.available(Reg) && !MRI.isReserved(Reg) &&
887 static Register buildScratchExecCopy(LiveRegUnits &LiveUnits,
900 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, IsProlog);
903 MRI, LiveUnits, *TRI.getWaveMaskRegClass());
907 LiveUnits.addReg(ScratchExecCopy);
923 MachineBasicBlock::iterator MBBI, DebugLoc &DL, LiveRegUnits &LiveUnits,
938 buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL,
946 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL,
957 ScratchExecCopy = buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL,
969 LiveUnits.addReg(ScratchExecCopy);
985 LiveUnits, FrameReg);
1000 if (!LiveUnits.empty()) {
1002 LiveUnits.addReg(Reg);
1009 MachineBasicBlock::iterator MBBI, DebugLoc &DL, LiveRegUnits &LiveUnits,
1029 LiveUnits, FrameReg);
1041 buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL,
1049 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MBBI, DL,
1060 ScratchExecCopy = buildScratchExecCopy(LiveUnits, MF, MBB, MBBI, DL,
1093 LiveRegUnits LiveUnits;
1123 emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits,
1131 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ true);
1139 DL, TII, TRI, LiveUnits, FramePtrReg);
1141 LiveUnits.addReg(SGPRForFPSaveRestoreCopy);
1146 MRI, LiveUnits, AMDGPU::SReg_32_XM0_XEXECRegClass);
1150 LiveUnits.addReg(FramePtrRegScratchCopy);
1160 if (LiveUnits.empty()) {
1161 LiveUnits.init(TRI);
1162 LiveUnits.addLiveIns(MBB);
1185 emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg,
1188 LiveUnits.removeReg(FramePtrRegScratchCopy);
1237 LiveRegUnits LiveUnits;
1279 initLiveUnits(LiveUnits, TRI, FuncInfo, MF, MBB, MBBI, /*IsProlog*/ false);
1281 LiveUnits.addReg(SGPRForFPSaveRestoreCopy);
1284 MRI, LiveUnits, AMDGPU::SReg_32_XM0_XEXECRegClass);
1288 LiveUnits.addReg(FramePtrRegScratchCopy);
1291 emitCSRSpillRestores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg,
1306 emitCSRSpillRestores(MF, MBB, MBBI, DL, LiveUnits,
1500 LiveRegUnits LiveUnits;
1501 LiveUnits.init(*TRI);
1506 LiveUnits.addReg(CSRegs[I]);
1515 Register UnusedScratchReg = findUnusedRegister(MRI, LiveUnits, RC);
1521 LiveUnits.addReg(UnusedScratchReg);
1526 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, ReservedRegForExecCopy, RC,
1551 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, FramePtrReg);
1558 getVGPRSpillLaneOrTempRegister(MF, LiveUnits, BasePtrReg);