Lines Matching defs:FramePtrReg

972   Register FramePtrReg = FuncInfo->getFrameOffsetReg();
980         Spill.first == FramePtrReg ? FramePtrRegScratchCopy : Spill.first;
1015   Register FramePtrReg = FuncInfo->getFrameOffsetReg();
1024         Spill.first == FramePtrReg ? FramePtrRegScratchCopy : Spill.first;
1090   Register FramePtrReg = FuncInfo->getFrameOffsetReg();
1129         FuncInfo->getScratchSGPRCopyDstReg(FramePtrReg);
1137           FramePtrReg,
1138           FuncInfo->getPrologEpilogSGPRSaveRestoreInfo(FramePtrReg), MBB, MBBI,
1139           DL, TII, TRI, LiveUnits, FramePtrReg);
1152           .addReg(FramePtrReg);
1167     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_I32), FramePtrReg)
1171     auto And = BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
1172         .addReg(FramePtrReg, RegState::Kill)
1178     BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
1185     emitCSRSpillStores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg,
1209   bool FPSaved = FuncInfo->hasPrologEpilogSGPRSpillEntry(FramePtrReg);
1256   Register FramePtrReg = FuncInfo->getFrameOffsetReg();
1257   bool FPSaved = FuncInfo->hasPrologEpilogSGPRSpillEntry(FramePtrReg);
1266           .addReg(FramePtrReg)
1273       FuncInfo->getScratchSGPRCopyDstReg(FramePtrReg);
1291     emitCSRSpillRestores(MF, MBB, MBBI, DL, LiveUnits, FramePtrReg,
1300         BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
1548     Register FramePtrReg = MFI->getFrameOffsetReg();
1549     assert(!MFI->hasPrologEpilogSGPRSpillEntry(FramePtrReg) &&
1551     getVGPRSpillLaneOrTempRegister(MF, LiveUnits, FramePtrReg);
1705   Register FramePtrReg = FuncInfo->getFrameOffsetReg();
1708       FuncInfo->getScratchSGPRCopyDstReg(FramePtrReg);
1722     if (CS.getReg() == FramePtrReg && SGPRForFPSaveRestoreCopy) {