Lines Matching defs:isReg

48       assert(FoldOp->isReg() || FoldOp->isGlobal());
61   bool isReg() const {
330   assert(Old.isReg() && Fold.isImm());
482   assert(Old.isReg());
693     if (!MI->getOperand(OpNo).isReg() || !MI->getOperand(CommuteOpNo).isReg())
711       if (!OtherOp.isReg() ||
729       !OpToFold->isReg() && !TII->isInlineConstant(*OpToFold)) {
732     if (!OpImm.isReg() &&
755     if (!OpToFold->isReg() && !TII->isInlineConstant(*OpToFold, OpInfo)) {
759         if (OpNo != i && !Op.isReg() &&
788     assert(Sub->isReg());
791          SubDef && Sub->isReg() && Sub->getReg().isVirtual() &&
800       if (!Op->isReg() || Op->getReg().isPhysical())
828   if (!OpToFold.isReg())
887   if (UseOp->isReg() && OpToFold.isReg() &&
1009     if (UseMI->isCopy() && OpToFold.isReg() &&
1052           } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
1065             assert(Def->isReg());
1130       if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
1160     if (OpToFold.isReg() && ST->needsAlignedVGPRs()) {
1299   if (!Op.isReg() || Op.getSubReg() != AMDGPU::NoSubRegister ||
1442       TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
1524     assert(!Fold.isReg() || Fold.OpToFold);
1525     if (Fold.isReg() && Fold.OpToFold->getReg().isVirtual()) {
1534       if (Fold.isReg()) {
1535         assert(Fold.OpToFold && Fold.OpToFold->isReg());
1565     CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical())
1583   if (!FoldingImm && !OpToFold.isReg())
1586   if (OpToFold.isReg() && !OpToFold.getReg().isVirtual())
1598   if (OpToFold.isReg() &&
1612     auto SrcReg = SrcOp.isReg() ? SrcOp.getReg() : Register();
1654     if (!Src0->isReg() || !Src1->isReg() ||
1840     if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
1860   if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
1911     if (!Op->isReg())