Lines Matching defs:Def
258 MachineInstr *Def = MRI->getVRegDef(SrcReg);
259 if (!Def || Def->getNumOperands() != 4)
262 MachineOperand *Src0 = &Def->getOperand(1);
263 MachineOperand *Src1 = &Def->getOperand(2);
275 unsigned NewOp = convertToVALUOp(Def->getOpcode(), UseVOP3);
277 !Def->getOperand(3).isDead()) // Check if scc is dead
280 MachineBasicBlock *MBB = Def->getParent();
281 const DebugLoc &DL = Def->getDebugLoc();
284 BuildMI(*MBB, *Def, DL, TII->get(NewOp), DstReg);
292 Add.add(*Src0).add(*Src1).setMIFlags(Def->getFlags());
296 Def->eraseFromParent();
304 MBB->computeRegisterLiveness(TRI, AMDGPU::VCC, *Def, 16);
307 BuildMI(*MBB, *Def, DL, TII->get(NewOp), DstReg)
311 .setMIFlags(Def->getFlags());
312 Def->eraseFromParent();
782 MachineInstr *Def = MRI->getVRegDef(UseReg);
783 if (!Def || !Def->isRegSequence())
786 for (unsigned I = 1, E = Def->getNumExplicitOperands(); I < E; I += 2) {
787 MachineOperand *Sub = &Def->getOperand(I);
805 Defs.emplace_back(Sub, Def->getOperand(I + 1).getImm());
839 MachineInstr *Def = MRI->getVRegDef(UseReg);
841 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) {
842 MachineOperand &DefOp = Def->getOperand(1);
1042 MachineOperand *Def = Defs[I].first;
1044 if (Def->isImm() &&
1045 TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
1046 int64_t Imm = Def->getImm();
1052 } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
1053 auto Src = getRegSubRegPair(*Def);
1054 Def->setIsKill(false);
1061 B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
1065 assert(Def->isReg());
1066 Def->setIsKill(false);
1067 auto Src = getRegSubRegPair(*Def);
1076 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
1087 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
1303 MachineInstr *Def = MRI->getVRegDef(Op.getReg());
1304 if (Def && Def->isMoveImmediate()) {
1305 MachineOperand &ImmSrc = Def->getOperand(1);
1688 MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());
1691 if (TII->getClampMask(*Def) != TII->getClampMask(MI))
1694 if (Def->mayRaiseFPException())
1697 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
1701 LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def);
1706 Register DefReg = Def->getOperand(0).getReg();
1722 if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
1723 Def->eraseFromParent();
1865 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());
1866 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);
1870 if (Def->mayRaiseFPException())
1875 if (TII->hasModifiersSet(*Def, AMDGPU::OpName::clamp))
1878 LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def);
1881 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1884 MRI->clearKillFlags(Def->getOperand(0).getReg());
1890 if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
1891 Def->eraseFromParent();
1948 for (auto &[Def, SubIdx] : Defs) {
1949 Def->setIsKill(false);
1950 if (TRI->isAGPR(*MRI, Def->getReg())) {
1951 RS.add(*Def);
1953 MachineInstr *SubDef = MRI->getVRegDef(Def->getReg());
1955 RS.addReg(SubDef->getOperand(1).getReg(), 0, Def->getSubReg());
2091 if (MachineInstr *Def = MRI->getVRegDef(Reg)) {
2095 if (Def->isCopy()) {
2098 if (isAGPRCopy(*TRI, *MRI, *Def, AGPRSrc, AGPRSubReg)) {
2110 MachineOperand &CopyIn = Def->getOperand(1);
2116 InsertMBB = Def->getParent();
2117 InsertPt = InsertMBB->SkipPHIsLabelsAndDebug(++Def->getIterator());
2154 MachineOperand &Def = MI.getOperand(0);
2155 if (!Def.isDef())
2158 Register DefReg = Def.getReg();
2189 if (!TII->isOperandLegal(MI, 0, &Def)) {
2269 MachineInstr *Def = MRI->getVRegDef(Reg);
2270 MachineBasicBlock *DefMBB = Def->getParent();
2278 BuildMI(*DefMBB, ++Def->getIterator(), Def->getDebugLoc(),
2284 BuildMI(*DefMBB, ++VGPRCopy->getIterator(), Def->getDebugLoc(),