Lines Matching defs:MemVT

1038   EVT MemVT = Store->getMemoryVT();
1071   SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1112   EVT MemVT = StoreNode->getMemoryVT();
1128           NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT,
1138   if (Alignment < MemVT.getStoreSize() &&
1139       !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment,
1154       if (MemVT == MVT::i8) {
1157         assert(MemVT == MVT::i16);
1185                                      Op->getVTList(), Args, MemVT,
1205   if (MemVT.bitsLT(MVT::i32))
1265   EVT MemVT = Load->getMemoryVT();
1266   assert(Load->getAlign() >= MemVT.getStoreSize());
1299   EVT MemEltVT = MemVT.getScalarType();
1319   EVT MemVT = LoadNode->getMemoryVT();
1323       ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) {
1379     assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1381         ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1384                               DAG.getValueType(MemVT));
1473     EVT MemVT = VA.getLocVT();
1474     if (!VT.isVector() && MemVT.isVector()) {
1476       MemVT = MemVT.getVectorElementType();
1494     if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1514         MemVT, Alignment, MachineMemOperand::MONonTemporal |
1530 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1534     return (MemVT.getSizeInBits() <= 32);