Lines Matching full:imm
60 int64_t Imm = Op.getImm();
61 if (isInt<16>(Imm) || isUInt<16>(Imm))
62 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
88 uint32_t Imm = MI->getOperand(OpNo).getImm();
89 if (Imm != 0) {
96 O << formatDec(SignExtend32<24>(Imm));
105 uint32_t Imm = MI->getOperand(OpNo).getImm();
106 if (Imm != 0) {
115 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI)));
141 auto Imm = MI->getOperand(OpNo).getImm();
144 const int64_t TH = Imm & CPol::TH;
145 const int64_t Scope = Imm & CPol::SCOPE;
153 if (Imm & CPol::GLC)
157 if (Imm & CPol::SLC)
159 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
161 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
163 if (Imm & ~CPol::ALL_pregfx12)
402 void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
405 int32_t SImm = static_cast<int32_t>(Imm);
411 if (printImmediateFloat32(Imm, STI, O))
414 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
417 static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI,
419 if (Imm == 0x3C00)
421 else if (Imm == 0xBC00)
423 else if (Imm == 0x3800)
425 else if (Imm == 0xB800)
427 else if (Imm == 0x4000)
429 else if (Imm == 0xC000)
431 else if (Imm == 0x4400)
433 else if (Imm == 0xC400)
435 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
443 static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI,
445 if (Imm == 0x3F80)
447 else if (Imm == 0xBF80)
449 else if (Imm == 0x3F00)
451 else if (Imm == 0xBF00)
453 else if (Imm == 0x4000)
455 else if (Imm == 0xC000)
457 else if (Imm == 0x4080)
459 else if (Imm == 0xC080)
461 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
469 void AMDGPUInstPrinter::printImmediateBF16(uint32_t Imm,
472 int16_t SImm = static_cast<int16_t>(Imm);
478 if (printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
481 O << formatHex(static_cast<uint64_t>(Imm));
484 void AMDGPUInstPrinter::printImmediateF16(uint32_t Imm,
487 int16_t SImm = static_cast<int16_t>(Imm);
493 uint16_t HImm = static_cast<uint16_t>(Imm);
497 uint64_t Imm16 = static_cast<uint16_t>(Imm);
501 void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, uint8_t OpType,
504 int32_t SImm = static_cast<int32_t>(Imm);
514 if (printImmediateFloat32(Imm, STI, O))
520 if (isUInt<16>(Imm) &&
521 printImmediateFP16(static_cast<uint16_t>(Imm), STI, O))
527 if (isUInt<16>(Imm) &&
528 printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
535 O << formatHex(static_cast<uint64_t>(Imm));
538 bool AMDGPUInstPrinter::printImmediateFloat32(uint32_t Imm,
541 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
543 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
545 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
547 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
549 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
551 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
553 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
555 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
557 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
559 else if (Imm == 0x3e22f983 &&
568 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
571 int32_t SImm = static_cast<int32_t>(Imm);
577 if (printImmediateFloat32(Imm, STI, O))
580 O << formatHex(static_cast<uint64_t>(Imm));
583 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
586 int64_t SImm = static_cast<int64_t>(Imm);
592 if (Imm == llvm::bit_cast<uint64_t>(0.0))
594 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
596 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
598 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
600 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
602 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
604 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
606 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
608 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
610 else if (Imm == 0x3fc45f306dc9c882 &&
614 assert(AMDGPU::isValid32BitLiteral(Imm, true));
615 O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
617 assert(isUInt<32>(Imm) || isInt<32>(Imm));
621 O << formatHex(static_cast<uint64_t>(Imm));
628 unsigned Imm = MI->getOperand(OpNo).getImm();
629 if (!Imm)
638 O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
639 << ((Imm >> 2) & 1) << ']';
644 O << " blgp:" << Imm;
706 // for example sgpr register used in VReg or VISrc(VReg or imm) operand.
953 unsigned Imm = MI->getOperand(OpNo).getImm();
954 O << "dpp8:[" << formatDec(Imm & 0x7);
956 O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
966 unsigned Imm = MI->getOperand(OpNo).getImm();
969 if (!AMDGPU::isLegalDPALU_DPPControl(Imm) && AMDGPU::isDPALU_DPP(Desc)) {
973 if (Imm <= DppCtrl::QUAD_PERM_LAST) {
975 O << formatDec(Imm & 0x3) << ',';
976 O << formatDec((Imm & 0xc) >> 2) << ',';
977 O << formatDec((Imm & 0x30) >> 4) << ',';
978 O << formatDec((Imm & 0xc0) >> 6) << ']';
979 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
980 (Imm <= DppCtrl::ROW_SHL_LAST)) {
981 O << "row_shl:" << formatDec(Imm - DppCtrl::ROW_SHL0);
982 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
983 (Imm <= DppCtrl::ROW_SHR_LAST)) {
984 O << "row_shr:" << formatDec(Imm - DppCtrl::ROW_SHR0);
985 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
986 (Imm <= DppCtrl::ROW_ROR_LAST)) {
987 O << "row_ror:" << formatDec(Imm - DppCtrl::ROW_ROR0);
988 } else if (Imm == DppCtrl::WAVE_SHL1) {
994 } else if (Imm == DppCtrl::WAVE_ROL1) {
1000 } else if (Imm == DppCtrl::WAVE_SHR1) {
1006 } else if (Imm == DppCtrl::WAVE_ROR1) {
1012 } else if (Imm == DppCtrl::ROW_MIRROR) {
1014 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
1016 } else if (Imm == DppCtrl::BCAST15) {
1022 } else if (Imm == DppCtrl::BCAST31) {
1028 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
1029 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
1039 O << formatDec(Imm - DppCtrl::ROW_SHARE_FIRST);
1040 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
1041 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1046 O << "row_xmask:" << formatDec(Imm - DppCtrl::ROW_XMASK_FIRST);
1055 unsigned Imm = MI->getOperand(OpNo).getImm();
1056 if (Imm) {
1064 unsigned Imm = MI->getOperand(OpNo).getImm();
1065 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1074 unsigned Imm = MI->getOperand(OpNo).getImm();
1075 switch (Imm) {
1114 unsigned Imm = MI->getOperand(OpNo).getImm();
1115 switch (Imm) {
1314 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1315 if (Imm == 0)
1318 O << " index_key:" << Imm;
1324 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1325 if (Imm == 0)
1328 O << " index_key:" << Imm;
1334 unsigned Imm = MI->getOperand(OpNum).getImm();
1335 switch (Imm) {
1346 O << "invalid_param_" << Imm;
1418 int Imm = MI->getOperand(OpNo).getImm();
1419 if (Imm == SIOutMods::MUL2)
1421 else if (Imm == SIOutMods::MUL4)
1423 else if (Imm == SIOutMods::DIV2)
1496 uint16_t Imm = MI->getOperand(OpNo).getImm();
1497 if (Imm == 0) {
1504 if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
1505 if (Imm >= FFT_MODE_LO) {
1506 O << "swizzle(" << IdSymbolic[ID_FFT] << ',' << (Imm & FFT_SWIZZLE_MASK)
1508 } else if (Imm >= ROTATE_MODE_LO) {
1510 << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ','
1511 << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ')';
1517 if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
1521 O << formatDec(Imm & LANE_MASK);
1522 Imm >>= LANE_SHIFT;
1526 } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1528 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1529 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1530 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1700 uint16_t Imm = MI->getOperand(OpNo).getImm();
1701 if (Imm == 0) {
1705 O << ' ' << formatDec(Imm);
1720 uint8_t Imm = MI->getOperand(OpNo).getImm();
1721 if (!Imm)
1725 if (Imm <= 10)
1726 O << formatDec(Imm);
1728 O << formatHex(static_cast<uint64_t>(Imm));