Lines Matching defs:STI
43 StringRef Annot, const MCSubtargetInfo &STI,
45 printInstruction(MI, Address, STI, OS);
50 const MCSubtargetInfo &STI,
64 printU32ImmOperand(MI, OpNo, STI, O);
73 const MCSubtargetInfo &STI,
86 const MCSubtargetInfo &STI,
95 if (AMDGPU::isGFX12(STI) && IsVBuffer)
103 const MCSubtargetInfo &STI,
112 AMDGPU::isGFX12(STI);
115 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI)));
122 const MCSubtargetInfo &STI,
124 printU32ImmOperand(MI, OpNo, STI, O);
128 const MCSubtargetInfo &STI,
134 const MCSubtargetInfo &STI,
136 printU32ImmOperand(MI, OpNo, STI, O);
140 const MCSubtargetInfo &STI, raw_ostream &O) {
143 if (AMDGPU::isGFX12Plus(STI)) {
154 O << ((AMDGPU::isGFX940(STI) &&
158 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
159 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
161 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
162 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
249 const MCSubtargetInfo &STI, raw_ostream &O) {
261 const MCSubtargetInfo &STI, raw_ostream &O) {
262 if (STI.hasFeature(AMDGPU::FeatureR128A16))
269 const MCSubtargetInfo &STI,
274 const MCSubtargetInfo &STI,
283 if (AMDGPU::isGFX10Plus(STI)) {
286 if (isValidUnifiedFormat(Val, STI)) {
287 O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
294 if (isValidDfmtNfmt(Val, STI)) {
306 O << getNfmtName(Nfmt, STI);
332 const MCSubtargetInfo &STI, raw_ostream &O) {
351 printRegularOperand(MI, OpNo, STI, O);
387 printDefaultVccOperand(false, STI, O);
393 const MCSubtargetInfo &STI, raw_ostream &O) {
394 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
399 printRegularOperand(MI, OpNo, STI, O);
403 const MCSubtargetInfo &STI,
411 if (printImmediateFloat32(Imm, STI, O))
417 static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI,
435 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
443 static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI,
461 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
470 const MCSubtargetInfo &STI,
478 if (printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
485 const MCSubtargetInfo &STI,
494 if (printImmediateFP16(HImm, STI, O))
502 const MCSubtargetInfo &STI,
514 if (printImmediateFloat32(Imm, STI, O))
521 printImmediateFP16(static_cast<uint16_t>(Imm), STI, O))
528 printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
539 const MCSubtargetInfo &STI,
560 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
569 const MCSubtargetInfo &STI,
577 if (printImmediateFloat32(Imm, STI, O))
584 const MCSubtargetInfo &STI,
611 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
626 const MCSubtargetInfo &STI,
632 if (AMDGPU::isGFX940(STI)) {
648 const MCSubtargetInfo &STI,
652 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize32)
671 const MCSubtargetInfo &STI,
684 printDefaultVccOperand(true, STI, O);
686 printRegularOperand(MI, OpNo, STI, O);
691 const MCSubtargetInfo &STI,
732 printImmediate32(Op.getImm(), STI, O);
736 printImmediate64(Op.getImm(), STI, O, false);
741 printImmediate64(Op.getImm(), STI, O, true);
746 printImmediateInt16(Op.getImm(), STI, O);
752 printImmediateF16(Op.getImm(), STI, O);
758 printImmediateBF16(Op.getImm(), STI, O);
769 printImmediateV216(Op.getImm(), OpTy, STI, O);
778 printImmediate32(Op.getImm(), STI, O);
796 printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O);
798 printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O, true);
852 printDefaultVccOperand(OpNo == 0, STI, O);
861 printSymbolicFormat(MI, STI, O);
867 const MCSubtargetInfo &STI,
871 printDefaultVccOperand(true, STI, O);
895 printRegularOperand(MI, OpNo + 1, STI, O);
913 printDefaultVccOperand(OpNo == 0, STI, O);
920 const MCSubtargetInfo &STI,
924 printDefaultVccOperand(true, STI, O);
929 printRegularOperand(MI, OpNo + 1, STI, O);
942 printDefaultVccOperand(OpNo == 0, STI, O);
948 const MCSubtargetInfo &STI,
950 if (!AMDGPU::isGFX10Plus(STI))
962 const MCSubtargetInfo &STI,
989 if (AMDGPU::isGFX10Plus(STI)) {
995 if (AMDGPU::isGFX10Plus(STI)) {
1001 if (AMDGPU::isGFX10Plus(STI)) {
1007 if (AMDGPU::isGFX10Plus(STI)) {
1017 if (AMDGPU::isGFX10Plus(STI)) {
1023 if (AMDGPU::isGFX10Plus(STI)) {
1030 if (AMDGPU::isGFX90A(STI)) {
1032 } else if (AMDGPU::isGFX10Plus(STI)) {
1042 if (!AMDGPU::isGFX10Plus(STI)) {
1053 const MCSubtargetInfo &STI,
1062 const MCSubtargetInfo &STI, raw_ostream &O) {
1088 const MCSubtargetInfo &STI,
1095 const MCSubtargetInfo &STI,
1102 const MCSubtargetInfo &STI,
1109 const MCSubtargetInfo &STI,
1124 const MCSubtargetInfo &STI, raw_ostream &O,
1143 const MCSubtargetInfo &STI,
1145 printExpSrcN(MI, OpNo, STI, O, 0);
1149 const MCSubtargetInfo &STI,
1151 printExpSrcN(MI, OpNo, STI, O, 1);
1155 const MCSubtargetInfo &STI,
1157 printExpSrcN(MI, OpNo, STI, O, 2);
1161 const MCSubtargetInfo &STI,
1163 printExpSrcN(MI, OpNo, STI, O, 3);
1167 const MCSubtargetInfo &STI,
1176 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1267 const MCSubtargetInfo &STI,
1294 const MCSubtargetInfo &STI,
1300 const MCSubtargetInfo &STI,
1306 const MCSubtargetInfo &STI,
1312 const MCSubtargetInfo &STI,
1322 const MCSubtargetInfo &STI,
1332 const MCSubtargetInfo &STI,
1351 const MCSubtargetInfo &STI,
1358 const MCSubtargetInfo &STI,
1365 const MCSubtargetInfo &STI,
1388 const MCSubtargetInfo &STI,
1390 printRegularOperand(MI, OpNo, STI, O);
1392 printRegularOperand(MI, OpNo + 1, STI, O);
1416 const MCSubtargetInfo &STI,
1428 const MCSubtargetInfo &STI,
1437 decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
1439 StringRef MsgName = getMsgName(MsgId, STI);
1441 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1442 isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1444 if (msgRequiresOp(MsgId, STI)) {
1445 O << ", " << getMsgOpName(MsgId, OpId, STI);
1446 if (msgSupportsStream(MsgId, OpId, STI)) {
1492 const MCSubtargetInfo &STI,
1504 if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
1575 const MCSubtargetInfo &STI,
1577 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());
1610 const MCSubtargetInfo &STI,
1617 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1623 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1637 const MCSubtargetInfo &STI,
1680 const MCSubtargetInfo &STI, raw_ostream &O) {
1684 StringRef HwRegName = getHwreg(Id, STI);
1698 const MCSubtargetInfo &STI,
1709 const MCSubtargetInfo &STI,
1718 const MCSubtargetInfo &STI,