Lines Matching defs:VALU

687   // SGPR was written by a VALU instruction.
732 // SGPR was written by a VALU Instruction.
753 // Check for DPP VGPR read after VALU VGPR write and EXEC write.
783 // v_div_fmas requires 4 wait states after a write to vcc from a VALU
951 static bool consumesDstSelForwardingOperand(const MachineInstr *VALU,
954 // We must consider implicit reads of the VALU. SDWA with dst_sel and
964 for (auto &Operand : VALU->operands()) {
972 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) {
975 if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) {
978 auto IsTransDefFn = [this, VALU](const MachineInstr &MI) {
985 for (const MachineOperand &Use : VALU->explicit_uses()) {
1002 auto IsShift16BitDefFn = [this, VALU](const MachineInstr &ProducerMI) {
1007 return consumesDstSelForwardingOperand(VALU, ForwardedDst, TRI);
1013 if (consumesDstSelForwardingOperand(VALU, &Def, TRI))
1041 for (const MachineOperand &Use : VALU->explicit_uses()) {
1055 if (VALU->readsRegister(AMDGPU::VCC, TRI)) {
1063 switch (VALU->getOpcode()) {
1066 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0);
1094 for (const MachineOperand &Def : VALU->defs()) {
1559 // This makes va_vdst count unusable with a mixture of VALU and TRANS.
1630 // Va <- VALU [PreExecPos]
1634 // Vb <- VALU [PostExecPos]
1659 // Too many VALU states have passed
1775 // Va <- TRANS VALU
1796 // Too many VALU states have passed
2677 // Only hazard if register is defined by a VALU and a DGEMM is found after
2724 // is a DGEMM instruction in-between a VALU and a VMEM instruction it
2991 // 1. VALU reads SGPR as mask
3054 // VALU access to any SGPR or literal constant other than HazardReg
3157 // hazard insertion when all VALU access to an SGPR occurs after its last
3207 // 1. VALU reads SGPR
3209 // 3. VALU/SALU reads SGPR
3263 // Collect all SGPR sources for MI which are read by a VALU.
3341 // A hazard is any VALU which reads one of the paired SGPRs read by MI.