Lines Matching defs:MaxWaitStates

2107     const int MaxWaitStates = 4;
2110       getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates);
2113     if (WaitStatesNeeded < MaxWaitStates) {
2115         const int MaxWaitStates = 2;
2121           getWaitStatesSinceDef(Use.getReg(), IsVALUFn, MaxWaitStates);
2124         if (WaitStatesNeeded == MaxWaitStates)
2145     const int MaxWaitStates = 18;
2162                                                    MaxWaitStates);
2193     if (WaitStatesNeeded == MaxWaitStates)
2213       getWaitStatesSinceDef(Reg, IsAccVgprWriteFn, MaxWaitStates);
2216     if (WaitStatesNeeded == MaxWaitStates)
2224     const int MaxWaitStates = 13;
2238     int WaitStatesSince = getWaitStatesSince(IsSrcCMFMAFn, MaxWaitStates);
2352     const int MaxWaitStates = 19;
2371       getWaitStatesSinceDef(Reg, IsLegacyVALUNotDotFn, MaxWaitStates);
2375         getWaitStatesSinceDef(Reg, IsOverlappedMFMAFn, MaxWaitStates);
2501     if (WaitStatesNeeded == MaxWaitStates)
2530     const int MaxWaitStates = 2;
2533       getWaitStatesSinceDef(Reg, IsAccVgprReadFn, MaxWaitStates);
2536     if (WaitStatesNeeded == MaxWaitStates)
2546       return getWaitStatesSinceDef(Reg, IsVALUFn, 2 /*MaxWaitStates*/) <
2551       getWaitStatesSince(IsVALUAccVgprRdWrCheckFn, MaxWaitStates);
2584                               /*MaxWaitStates=*/VALUWritesVDstWaitStates);
2700     const int MaxWaitStates = 19;
2709                                                      MaxWaitStates);
2741           getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates);
2747       int NeedWaitStates = MaxWaitStates;
2792       if (WaitStatesNeeded == MaxWaitStates)
2822     const int MaxWaitStates = 19;
2829                                                    MaxWaitStates);
2836         getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates);
2838       int NeedWaitStates = MaxWaitStates;
2877       if (WaitStatesNeeded == MaxWaitStates)
2906     int NeedWaitStates = MaxWaitStates;