Lines Matching defs:OrigMI

64   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
69   MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI,
209 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
219   auto OrigOp = OrigMI.getOpcode();
239   auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
240                          OrigMI.getDebugLoc(), TII->get(DPPOp))
241     .setMIFlags(OrigMI.getFlags());
246     if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) {
250     if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) {
282     auto *Mod0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0_modifiers);
306     auto *Mod1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1_modifiers);
318     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
339     auto *Mod2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers);
348     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);
361       auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);
365       auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);
370       auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);
376       if (TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) {
381         if (Mod0 && TII->isVOP3(OrigMI) && !TII->isVOP3P(OrigMI))
392       if (TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) {
409       auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);
413       auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);
417       auto *ByteSelOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::byte_sel);
490     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
494     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
499     if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {
511   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);
639     auto &OrigMI = *Use->getParent();
640     LLVM_DEBUG(dbgs() << "  try: " << OrigMI);
642     auto OrigOp = OrigMI.getOpcode();
646       Register FwdReg = OrigMI.getOperand(0).getReg();
649       if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) {
655       unsigned OpNo, E = OrigMI.getNumOperands();
657         if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
658           FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();
670       RegSeqWithOpNos[&OrigMI].push_back(OpNo);
674     bool IsShrinkable = isShrinkable(OrigMI);
683     if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) {
688     auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);
689     auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
690     if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
695     auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2);
703           << "  " << OrigMI
708     LLVM_DEBUG(dbgs() << "  combining: " << OrigMI);
710       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
716       assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]
717       auto *BB = OrigMI.getParent();
718       auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
719       BB->insert(OrigMI, NewMI);
734     OrigMIs.push_back(&OrigMI);