Lines Matching defs:DPPInst

239   auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
247       DPPInst.add(*Dst);
251       if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) {
252         DPPInst.add(*SDst);
267       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
288       DPPInst.addImm(Mod0->getImm());
291       DPPInst.addImm(0);
297     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
302     DPPInst.add(*Src0);
303     DPPInst->getOperand(NumOperands).setIsKill(false);
312       DPPInst.addImm(Mod1->getImm());
315       DPPInst.addImm(0);
325         assert(getOperandSize(*DPPInst, Src0Idx, *MRI) ==
326                    getOperandSize(*DPPInst, NumOperands, *MRI) &&
330       if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) {
335       DPPInst.add(*Src1);
345       DPPInst.addImm(Mod2->getImm());
350       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
351           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
356       DPPInst.add(*Src2);
363         DPPInst.addImm(ClampOpr->getImm());
368         DPPInst.add(*VdstInOpr);
372         DPPInst.addImm(OmodOpr->getImm());
390           DPPInst.addImm(OpSel);
407           DPPInst.addImm(OpSelHi);
411         DPPInst.addImm(NegOpr->getImm());
415         DPPInst.addImm(NegHiOpr->getImm());
420         DPPInst.addImm(ByteSelOpr->getImm());
423     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
424     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
425     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));
426     DPPInst.addImm(CombBCZ ? 1 : 0);
430     DPPInst.getInstr()->eraseFromParent();
433   LLVM_DEBUG(dbgs() << "  combined:  " << *DPPInst.getInstr());
434   return DPPInst.getInstr();
710       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
712         DPPMIs.push_back(DPPInst);
722         if (auto *DPPInst =
725           DPPMIs.push_back(DPPInst);