Lines Matching defs:CombOldVGPR
65 RegSubRegPair CombOldVGPR,
70 RegSubRegPair CombOldVGPR, bool CombBCZ,
211 RegSubRegPair CombOldVGPR,
262 CombOldVGPR,
266 auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);
267 DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
268 CombOldVGPR.SubReg);
490 MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,
492 assert(CombOldVGPR.Reg);
503 CombOldVGPR = getRegSubRegPair(*Src1);
506 if (!isOfRegClass(CombOldVGPR, *RC, *MRI)) {
511 return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);
616 auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
618 if (CombBCZ && OldOpndValue) { // CombOldVGPR should be undef
620 CombOldVGPR = RegSubRegPair(
623 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
710 if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
723 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,