Lines Matching defs:decodeSrcOp
161 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
165 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize,
173 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral,
177 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
184 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
189 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,
198 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0,
203 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
208 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0,
212 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
218 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0,
232 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,
237 // and decode using 'enum10' from decodeSrcOp.
243 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,
252 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,
443 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
459 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,
1652 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val,
1899 ? decodeSrcOp(OPW32, Val)
1900 : decodeSrcOp(OPW64, Val);
1904 return decodeSrcOp(OPW32, Val);