Lines Matching defs:createRegOperand

151         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
757         MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i]));
850       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
1306 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
1311 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
1317   return createRegOperand(RegCl.getRegister(Val));
1367   return createRegOperand(SRegClassID, Val >> shift);
1373   return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16);
1664     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1733   return createRegOperand(getVgprClassId(Width), Val);
1741   case 102: return createRegOperand(FLAT_SCR_LO);
1742   case 103: return createRegOperand(FLAT_SCR_HI);
1743   case 104: return createRegOperand(XNACK_MASK_LO);
1744   case 105: return createRegOperand(XNACK_MASK_HI);
1745   case 106: return createRegOperand(VCC_LO);
1746   case 107: return createRegOperand(VCC_HI);
1747   case 108: return createRegOperand(TBA_LO);
1748   case 109: return createRegOperand(TBA_HI);
1749   case 110: return createRegOperand(TMA_LO);
1750   case 111: return createRegOperand(TMA_HI);
1752     return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);
1754     return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);
1755   case 126: return createRegOperand(EXEC_LO);
1756   case 127: return createRegOperand(EXEC_HI);
1757   case 235: return createRegOperand(SRC_SHARED_BASE_LO);
1758   case 236: return createRegOperand(SRC_SHARED_LIMIT_LO);
1759   case 237: return createRegOperand(SRC_PRIVATE_BASE_LO);
1760   case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO);
1761   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1762   case 251: return createRegOperand(SRC_VCCZ);
1763   case 252: return createRegOperand(SRC_EXECZ);
1764   case 253: return createRegOperand(SRC_SCC);
1765   case 254: return createRegOperand(LDS_DIRECT);
1776   case 102: return createRegOperand(FLAT_SCR);
1777   case 104: return createRegOperand(XNACK_MASK);
1778   case 106: return createRegOperand(VCC);
1779   case 108: return createRegOperand(TBA);
1780   case 110: return createRegOperand(TMA);
1783       return createRegOperand(SGPR_NULL);
1787       return createRegOperand(SGPR_NULL);
1789   case 126: return createRegOperand(EXEC);
1790   case 235: return createRegOperand(SRC_SHARED_BASE);
1791   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1792   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1793   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1794   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1795   case 251: return createRegOperand(SRC_VCCZ);
1796   case 252: return createRegOperand(SRC_EXECZ);
1797   case 253: return createRegOperand(SRC_SCC);
1809       return createRegOperand(SGPR_NULL);
1813       return createRegOperand(SGPR_NULL);
1834       return createRegOperand(getVgprClassId(Width),
1860     return createRegOperand(getVgprClassId(Width), Val);
1894   return createRegOperand(IsWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);