Lines Matching defs:OpWidth

154 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral,         \
161                       DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
166                                 AMDGPUDisassembler::OpWidthTy OpWidth,
173   return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral,
179 #define DECODE_OPERAND_REG_7(RegClass, OpWidth)                                \
180   DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
186 template <AMDGPUDisassembler::OpWidthTy OpWidth>
189   return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,
194 template <AMDGPUDisassembler::OpWidthTy OpWidth>
198   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0,
205 template <AMDGPUDisassembler::OpWidthTy OpWidth>
208   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0,
214 template <AMDGPUDisassembler::OpWidthTy OpWidth>
218   return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0,
227 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
232   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,
238 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
243   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,
247 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
252   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,
317 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
331                               OpWidth, Imm & 0xFF, false, ImmWidth,
335 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
350                               OpWidth, Imm & 0xFF, true, ImmWidth,
354 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
368                               OpWidth, Imm & 0xFF, false, ImmWidth,