Lines Matching defs:ImmWidth

155                      ImmWidth)                                                 \
162                                         MandatoryLiteral, ImmWidth));          \
168                                 bool MandatoryLiteral, unsigned ImmWidth,
174                                             ImmWidth, Sema));
225 // decoded into constant of size ImmWidth, should match width of immediate used
227 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
232   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,
238 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
243   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,
247 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
252   return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,
317 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
331                               OpWidth, Imm & 0xFF, false, ImmWidth,
335 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
350                               OpWidth, Imm & 0xFF, true, ImmWidth,
354 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
368                               OpWidth, Imm & 0xFF, false, ImmWidth,
1523 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm,
1529   // ImmWidth 0 is a default case where operand should not allow immediates.
1532   switch (ImmWidth) {
1654                                           unsigned ImmWidth,
1667   return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth,
1673                                        bool MandatoryLiteral, unsigned ImmWidth,
1695     return decodeFPImmed(ImmWidth, Val, Sema);
1823                                   unsigned ImmWidth,
1855       return decodeFPImmed(ImmWidth, SVal, Sema);