Lines Matching defs:Imm
88 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm,
94 int64_t Offset = SignExtend64<16>(Imm) * 4 + 4 + Addr;
98 return addOperand(Inst, MCOperand::createImm(Imm));
101 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
106 Offset = SignExtend64<24>(Imm);
108 Offset = Imm & 0xFFFFF;
110 Offset = SignExtend64<21>(Imm);
135 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
139 return addOperand(Inst, DAsm->DecoderName(Imm)); \
142 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
146 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
148 assert(Imm < (1 << 8) && "8-bit encoding"); \
151 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
156 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
158 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
167 unsigned Imm, unsigned EncImm,
171 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!");
177 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
180 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
182 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
183 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
184 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
187 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
189 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR,
195 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
198 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0,
203 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
206 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
208 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0,
212 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
213 // Imm{9} is acc, registers only.
215 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
218 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0,
229 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm,
232 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth,
236 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
240 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm,
243 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth,
249 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm,
252 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth,
294 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
297 assert(isUInt<10>(Imm) && "10-bit encoding expected");
298 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
300 bool IsHi = Imm & (1 << 9);
301 unsigned RegIdx = Imm & 0xff;
307 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
309 assert(isUInt<8>(Imm) && "8-bit encoding expected");
311 bool IsHi = Imm & (1 << 7);
312 unsigned RegIdx = Imm & 0x7f;
319 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
322 assert(isUInt<9>(Imm) && "9-bit encoding expected");
325 if (Imm & AMDGPU::EncValues::IS_VGPR) {
326 bool IsHi = Imm & (1 << 7);
327 unsigned RegIdx = Imm & 0x7f;
331 OpWidth, Imm & 0xFF, false, ImmWidth,
338 decodeOperand_VSrcT16_Lo128_Deferred(MCInst &Inst, unsigned Imm,
342 assert(isUInt<9>(Imm) && "9-bit encoding expected");
344 if (Imm & AMDGPU::EncValues::IS_VGPR) {
345 bool IsHi = Imm & (1 << 7);
346 unsigned RegIdx = Imm & 0x7f;
350 OpWidth, Imm & 0xFF, true, ImmWidth,
356 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
359 assert(isUInt<10>(Imm) && "10-bit encoding expected");
362 if (Imm & AMDGPU::EncValues::IS_VGPR) {
363 bool IsHi = Imm & (1 << 9);
364 unsigned RegIdx = Imm & 0xff;
368 OpWidth, Imm & 0xFF, false, ImmWidth,
372 static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm,
375 assert(isUInt<10>(Imm) && "10-bit encoding expected");
376 assert(Imm & AMDGPU::EncValues::IS_VGPR && "VGPR expected");
380 bool IsHi = Imm & (1 << 9);
381 unsigned RegIdx = Imm & 0xff;
385 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,
389 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
412 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
417 Imm &= 511;
433 Imm |= 512;
440 Imm |= 512;
443 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
447 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
450 return decodeAVLdSt(Inst, Imm, Opw, Decoder);
453 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm,
456 assert(Imm < (1 << 9) && "9-bit encoding");
459 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,
470 static DecodeStatus decodeVersionImm(MCInst &Inst, unsigned Imm,
474 return addOperand(Inst, DAsm->decodeVersionImm(Imm));
1408 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
1411 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1412 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
1413 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1414 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1418 static int64_t getInlineImmVal32(unsigned Imm) {
1419 switch (Imm) {
1443 static int64_t getInlineImmVal64(unsigned Imm) {
1444 switch (Imm) {
1468 static int64_t getInlineImmValF16(unsigned Imm) {
1469 switch (Imm) {
1493 static int64_t getInlineImmValBF16(unsigned Imm) {
1494 switch (Imm) {
1518 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) {
1519 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm)
1520 : getInlineImmValF16(Imm);
1523 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm,
1525 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN &&
1526 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
1530 // Imm value is still decoded into 32 bit immediate operand, inst printer will
1535 return MCOperand::createImm(getInlineImmVal32(Imm));
1537 return MCOperand::createImm(getInlineImmVal64(Imm));
1539 return MCOperand::createImm(getInlineImmVal16(Imm, Sema));
1913 MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const {
1920 auto [Version, W64, W32, MDP] = Encoding::decode(Imm);
1923 if (Encoding::encode(Version, W64, W32, MDP) != Imm)
1924 return MCOperand::createImm(Imm);