Lines Matching defs:DAsm

91   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
96   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
103   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
105   if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets.
107   } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
117   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
118   return addOperand(Inst, DAsm->decodeBoolReg(Val));
124   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
125   return addOperand(Inst, DAsm->decodeSplitBarrier(Val));
130   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
131   return addOperand(Inst, DAsm->decodeDpp8FI(Val));
138     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
139     return addOperand(Inst, DAsm->DecoderName(Imm));                           \
149     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
151         Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
159     auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
161                       DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
172   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
173   return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral,
302   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
303   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
313   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
314   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
324   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
328     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
330   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
341   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
347     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
349   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
361   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
365     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
367   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
378   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
382   return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
388   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
389   return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
394   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
395   return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
415   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
416   if (!DAsm->isGFX90A()) {
425     uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
428     const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
443   return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
457   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
459                     DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,
473   const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
474   return addOperand(Inst, DAsm->decodeVersionImm(Imm));