Lines Matching defs:AMDGPUDisassembler
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
19 #include "Disassembler/AMDGPUDisassembler.h"
48 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
53 // ToDo: AMDGPUDisassembler supports only VI ISA.
65 void AMDGPUDisassembler::setABIVersion(unsigned Version) {
91 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
103 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
117 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
124 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
130 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
138 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
149 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
159 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
161 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
166 AMDGPUDisassembler::OpWidthTy OpWidth,
172 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
186 template <AMDGPUDisassembler::OpWidthTy OpWidth>
194 template <AMDGPUDisassembler::OpWidthTy OpWidth>
205 template <AMDGPUDisassembler::OpWidthTy OpWidth>
214 template <AMDGPUDisassembler::OpWidthTy OpWidth>
227 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
238 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
247 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
302 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
313 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
317 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
324 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
335 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
341 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
354 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
361 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
378 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
388 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
394 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
413 AMDGPUDisassembler::OpWidthTy Opw,
415 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
446 template <AMDGPUDisassembler::OpWidthTy Opw>
457 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
459 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64,
473 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
513 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
807 void AMDGPUDisassembler::convertEXPInst(MCInst &MI) const {
816 void AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const {
840 void AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
882 void AMDGPUDisassembler::convertMAIInst(MCInst &MI) const {
950 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const {
985 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const {
1005 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const {
1012 void AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
1041 void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const {
1062 void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
1211 void AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const {
1239 void AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const {
1258 void AMDGPUDisassembler::convertVOPC64DPPInst(MCInst &MI) const {
1272 void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const {
1290 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
1296 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
1306 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
1311 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
1321 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
1370 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx,
1378 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const {
1391 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const {
1408 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
1523 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm,
1545 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
1571 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
1597 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
1621 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
1643 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1652 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val,
1672 AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val,
1724 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst,
1732 auto Width = llvm::AMDGPUDisassembler::OPW32;
1736 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1772 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1803 MCOperand AMDGPUDisassembler::decodeSpecialReg96Plus(unsigned Val) const {
1822 AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val,
1864 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1868 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1872 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1897 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1903 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const {
1907 MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const {
1913 MCOperand AMDGPUDisassembler::decodeVersionImm(unsigned Imm) const {
1948 bool AMDGPUDisassembler::isVI() const {
1952 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); }
1954 bool AMDGPUDisassembler::isGFX90A() const {
1958 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); }
1960 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); }
1962 bool AMDGPUDisassembler::isGFX10Plus() const {
1966 bool AMDGPUDisassembler::isGFX11() const {
1970 bool AMDGPUDisassembler::isGFX11Plus() const {
1974 bool AMDGPUDisassembler::isGFX12() const {
1978 bool AMDGPUDisassembler::isGFX12Plus() const {
1982 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const {
1986 bool AMDGPUDisassembler::hasKernargPreload() const {
2046 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(
2154 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2(
2202 Expected<bool> AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3(
2315 Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective(
2467 Expected<bool> AMDGPUDisassembler::decodeKernelDescriptor(
2507 Expected<bool> AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol,
2534 const MCExpr *AMDGPUDisassembler::createConstantSymbolExpr(StringRef Id,
2606 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());