Lines Matching defs:Operands
1407 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1607 OperandVector &Operands, MCStreamer &Out,
1611 ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
1615 SMLoc NameLoc, OperandVector &Operands) override;
1618 ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);
1623 parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1628 const char *Prefix, OperandVector &Operands,
1633 parseNamedBit(StringRef Name, OperandVector &Operands,
1636 ParseStatus parseCPol(OperandVector &Operands);
1637 ParseStatus parseScope(OperandVector &Operands, int64_t &Scope);
1638 ParseStatus parseTH(OperandVector &Operands, int64_t &TH);
1641 ParseStatus parseStringOrIntWithPrefix(OperandVector &Operands,
1645 ParseStatus parseStringOrIntWithPrefix(OperandVector &Operands,
1656 ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false,
1658 ParseStatus parseReg(OperandVector &Operands);
1659 ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false,
1661 ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,
1663 ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,
1665 ParseStatus parseRegWithFPInputMods(OperandVector &Operands);
1666 ParseStatus parseRegWithIntInputMods(OperandVector &Operands);
1667 ParseStatus parseVReg32OrOff(OperandVector &Operands);
1668 ParseStatus tryParseIndexKey(OperandVector &Operands,
1670 ParseStatus parseIndexKey8bit(OperandVector &Operands);
1671 ParseStatus parseIndexKey16bit(OperandVector &Operands);
1679 ParseStatus parseFORMAT(OperandVector &Operands);
1682 ParseStatus parseFlatOffset(OperandVector &Operands);
1683 ParseStatus parseR128A16(OperandVector &Operands);
1684 ParseStatus parseBLGP(OperandVector &Operands);
1688 void cvtExp(MCInst &Inst, const OperandVector &Operands);
1691 ParseStatus parseSWaitCnt(OperandVector &Operands);
1695 ParseStatus parseDepCtr(OperandVector &Operands);
1698 ParseStatus parseSDelayALU(OperandVector &Operands);
1700 ParseStatus parseHwreg(OperandVector &Operands);
1748 SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
1749 SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
1750 SMLoc getBLGPLoc(const OperandVector &Operands) const;
1753 const OperandVector &Operands) const;
1754 SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
1755 SMLoc getRegLoc(MCRegister Reg, const OperandVector &Operands) const;
1756 SMLoc getLitLoc(const OperandVector &Operands,
1758 SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;
1759 SMLoc getConstLoc(const OperandVector &Operands) const;
1760 SMLoc getInstLoc(const OperandVector &Operands) const;
1762 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1763 bool validateOffset(const MCInst &Inst, const OperandVector &Operands);
1764 bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1765 bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
1767 bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
1769 const OperandVector &Operands);
1773 bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
1777 bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
1781 bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
1783 bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
1784 bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
1785 bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
1786 bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
1789 bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
1790 bool validateDS(const MCInst &Inst, const OperandVector &Operands);
1791 bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
1793 bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
1794 bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
1796 bool validateTHAndScopeBits(const MCInst &Inst, const OperandVector &Operands,
1798 bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
1827 bool parseExpr(OperandVector &Operands);
1838 ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);
1840 ParseStatus parseExpTgt(OperandVector &Operands);
1841 ParseStatus parseSendMsg(OperandVector &Operands);
1842 ParseStatus parseInterpSlot(OperandVector &Operands);
1843 ParseStatus parseInterpAttr(OperandVector &Operands);
1844 ParseStatus parseSOPPBrTarget(OperandVector &Operands);
1845 ParseStatus parseBoolReg(OperandVector &Operands);
1854 ParseStatus parseSwizzle(OperandVector &Operands);
1865 ParseStatus parseGPRIdxMode(OperandVector &Operands);
1868 void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }
1869 void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }
1871 ParseStatus parseOModSI(OperandVector &Operands);
1873 void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1875 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1876 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1877 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1878 void cvtSWMMAC(MCInst &Inst, const OperandVector &Operands);
1880 void cvtVOPD(MCInst &Inst, const OperandVector &Operands);
1881 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
1883 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
1886 void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1887 void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1890 ParseStatus parseDim(OperandVector &Operands);
1892 ParseStatus parseDPP8(OperandVector &Operands);
1893 ParseStatus parseDPPCtrl(OperandVector &Operands);
1894 bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
1897 void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1898 void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
1899 cvtDPP(Inst, Operands, true);
1901 void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
1903 void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {
1904 cvtVOP3DPP(Inst, Operands, true);
1907 ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,
1909 ParseStatus parseSDWADstUnused(OperandVector &Operands);
1910 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1911 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1912 void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1913 void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1914 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1915 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1920 ParseStatus parseEndpgm(OperandVector &Operands);
1922 ParseStatus parseVOPD(OperandVector &Operands);
3160 ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
3173 ParseStatus S = parseImm(Operands, HasSP3AbsModifier, HasLit);
3211 Operands.push_back(
3214 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3241 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
3242 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3247 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
3256 ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
3262 Operands.push_back(std::move(R));
3268 ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
3270 ParseStatus Res = parseReg(Operands);
3275 return parseImm(Operands, HasSP3AbsMod, HasLit);
3367 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
3402 Res = parseRegOrImm(Operands, SP3Abs, Lit);
3404 Res = parseReg(Operands);
3409 if (Lit && !Operands.back()->isImm())
3427 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3436 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
3444 Res = parseRegOrImm(Operands);
3446 Res = parseReg(Operands);
3458 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
3467 ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {
3468 return parseRegOrImmWithFPInputMods(Operands, false);
3471 ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
3472 return parseRegOrImmWithIntInputMods(Operands, false);
3475 ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
3478 Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,
3488 Operands.push_back(std::move(Reg));
3747 const MCInst &Inst, const OperandVector &Operands) {
3828 SMLoc LitLoc = getLitLoc(Operands);
3829 SMLoc RegLoc = getRegLoc(LastSGPR, Operands);
3836 const MCInst &Inst, const OperandVector &Operands) {
3864 assert(ParsedIdx > 0 && ParsedIdx < Operands.size());
3866 auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();
4052 const OperandVector &Operands) {
4066 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4067 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4113 const OperandVector &Operands) {
4131 ErrLoc = getRegLoc(Reg, Operands);
4133 ErrLoc = getConstLoc(Operands);
4141 const OperandVector &Operands) {
4158 Error(getRegLoc(Reg, Operands),
4167 const OperandVector &Operands) {
4180 Error(getConstLoc(Operands),
4189 const OperandVector &Operands) {
4211 Operands),
4219 Operands),
4246 Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),
4462 SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
4463 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4464 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4472 const OperandVector &Operands) {
4480 return validateFlatOffset(Inst, Operands);
4483 return validateSMEMOffset(Inst, Operands);
4490 Error(getFlatOffsetLoc(Operands),
4497 Error(getFlatOffsetLoc(Operands),
4506 const OperandVector &Operands) {
4517 Error(getFlatOffsetLoc(Operands),
4529 Error(getFlatOffsetLoc(Operands),
4539 SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {
4541 for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
4542 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4550 const OperandVector &Operands) {
4573 Error(getSMEMOffsetLoc(Operands),
4694 const OperandVector &Operands) {
4703 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);
4719 SMLoc S = getRegLoc(Reg, Operands);
4724 Error(getInstLoc(Operands),
4743 const OperandVector &Operands) {
4774 Error(getLitLoc(Operands), "invalid operand for instruction");
4795 Error(getLitLoc(Operands), "literal operands are not supported");
4800 Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");
4880 SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {
4881 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4882 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4890 const OperandVector &Operands) {
4895 SMLoc BLGPLoc = getBLGPLoc(Operands);
4922 const OperandVector &Operands) {
4939 SMLoc RegLoc = getRegLoc(Reg, Operands);
4945 const OperandVector &Operands) {
4950 return validateGWS(Inst, Operands);
4960 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyGDS, Operands);
4970 const OperandVector &Operands) {
4987 SMLoc RegLoc = getRegLoc(Reg, Operands);
4996 const OperandVector &Operands,
5006 return validateTHAndScopeBits(Inst, Operands, CPol);
5011 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5026 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5046 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5060 const OperandVector &Operands,
5069 SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
5114 const OperandVector &Operands) {
5118 SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);
5119 if (Loc != getInstLoc(Operands)) {
5130 const OperandVector &Operands) {
5132 Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);
5136 Error(getLitLoc(Operands),
5140 if (!validateVOPLiteral(Inst, Operands)) {
5143 if (!validateConstantBusLimitations(Inst, Operands)) {
5146 if (!validateVOPDRegBankConstraints(Inst, Operands)) {
5150 Error(getImmLoc(AMDGPUOperand::ImmTyClamp, Operands),
5155 Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),
5160 Error(getImmLoc(AMDGPUOperand::ImmTyNegLo, Operands),
5165 Error(getImmLoc(AMDGPUOperand::ImmTyNegHi, Operands),
5169 if (!validateDPP(Inst, Operands)) {
5174 Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),
5178 if (!validateMIMGDim(Inst, Operands)) {
5183 Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),
5193 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
5198 Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
5202 if (!validateMovrels(Inst, Operands)) {
5205 if (!validateOffset(Inst, Operands)) {
5208 if (!validateMAIAccWrite(Inst, Operands)) {
5211 if (!validateMAISrc2(Inst, Operands)) {
5214 if (!validateMFMA(Inst, Operands)) {
5217 if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
5233 if (!validateDS(Inst, Operands)) {
5237 if (!validateBLGP(Inst, Operands)) {
5245 if (!validateWaitCnt(Inst, Operands)) {
5248 if (!validateTFE(Inst, Operands)) {
5324 static bool isInvalidVOPDY(const OperandVector &Operands,
5326 assert(InvalidOprIdx < Operands.size());
5327 const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);
5329 const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);
5336 OperandVector &Operands,
5344 auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
5361 if (!validateInstruction(Inst, IDLoc, Operands)) {
5369 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
5385 if (ErrorInfo >= Operands.size()) {
5388 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
5392 if (isInvalidVOPDY(Operands, ErrorInfo))
6360 ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,
6363 ParseStatus Res = parseVOPD(Operands);
6368 Res = MatchOperandParserImpl(Operands, Mnemonic);
6374 // are appending default values to the Operands list. This is only done
6382 unsigned Prefix = Operands.size();
6386 Res = parseReg(Operands);
6401 if (Operands.size() - Prefix > 1) {
6402 Operands.insert(Operands.begin() + Prefix,
6404 Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));
6410 return parseRegOrImm(Operands);
6449 OperandVector &Operands) {
6457 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));
6463 if (IsMIMG && isGFX10Plus() && Operands.size() == 2)
6465 ParseStatus Res = parseOperand(Operands, Name, Mode);
6493 OperandVector &Operands) {
6498 Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));
6512 const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
6525 Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));
6530 const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
6565 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));
6570 OperandVector &Operands,
6591 Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));
6615 ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
6626 ResTH = parseTH(Operands, TH);
6637 ResScope = parseScope(Operands, Scope);
6652 Operands.push_back(AMDGPUOperand::CreateImm(this, CPolVal, StringLoc,
6657 StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
6687 Operands.push_back(
6692 ParseStatus AMDGPUAsmParser::parseScope(OperandVector &Operands,
6698 Operands, "scope", {"SCOPE_CU", "SCOPE_SE", "SCOPE_DEV", "SCOPE_SYS"},
6707 ParseStatus AMDGPUAsmParser::parseTH(OperandVector &Operands, int64_t &TH) {
6769 MCInst& Inst, const OperandVector& Operands,
6776 ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);
6794 OperandVector &Operands, StringRef Name, ArrayRef<const char *> Ids,
6819 OperandVector &Operands, StringRef Name, ArrayRef<const char *> Ids,
6824 ParseStatus Res = parseStringOrIntWithPrefix(Operands, Name, Ids, IntVal);
6826 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S, Type));
6856 ParseStatus AMDGPUAsmParser::tryParseIndexKey(OperandVector &Operands,
6871 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, ImmTy));
6875 ParseStatus AMDGPUAsmParser::parseIndexKey8bit(OperandVector &Operands) {
6876 return tryParseIndexKey(Operands, AMDGPUOperand::ImmTyIndexKey8bit);
6879 ParseStatus AMDGPUAsmParser::parseIndexKey16bit(OperandVector &Operands) {
6880 return tryParseIndexKey(Operands, AMDGPUOperand::ImmTyIndexKey16bit);
7047 ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {
7061 Operands.push_back(
7074 Res = parseRegOrImm(Operands);
7085 auto Size = Operands.size();
7086 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[Size - 2]);
7098 ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {
7100 parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);
7102 Res = parseIntWithPrefix("inst_offset", Operands,
7108 ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {
7110 parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);
7112 Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);
7116 ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {
7118 parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);
7121 parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);
7130 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
7137 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
7138 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7185 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
7186 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
7265 ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
7280 Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));
7346 ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
7360 Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));
7433 ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
7450 Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));
7500 ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
7538 Operands.push_back(
7637 ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
7660 Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));
7672 ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
7688 Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,
7693 ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
7724 Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,
7726 Operands.push_back(AMDGPUOperand::CreateImm(
7735 ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
7750 Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,
7849 AMDGPUAsmParser::parseExpr(OperandVector &Operands) {
7858 Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
7860 Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
7927 SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {
7928 return ((AMDGPUOperand &)*Operands[0]).getStartLoc();
7933 const OperandVector &Operands) const {
7934 for (unsigned i = Operands.size() - 1; i > 0; --i) {
7935 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7939 return getInstLoc(Operands);
7944 const OperandVector &Operands) const {
7946 return getOperandLoc(Test, Operands);
7950 const OperandVector &Operands) const {
7954 return getOperandLoc(Test, Operands);
7957 SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,
7962 SMLoc Loc = getOperandLoc(Test, Operands);
7963 if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))
7964 Loc = getMandatoryLitLoc(Operands);
7968 SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {
7972 return getOperandLoc(Test, Operands);
7976 AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {
7980 return getOperandLoc(Test, Operands);
8305 ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
8320 Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));
8380 ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
8398 Operands.push_back(
8411 ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
8419 if (!parseExpr(Operands))
8422 AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);
8441 ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {
8442 return parseReg(Operands);
8450 const OperandVector &Operands,
8461 for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
8462 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
8492 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
8493 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
8623 ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
8626 return parseIntWithPrefix("mul", Operands,
8631 return parseIntWithPrefix("div", Operands,
8676 const OperandVector &Operands) {
8677 cvtVOP3P(Inst, Operands);
8681 void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
8683 cvtVOP3P(Inst, Operands, OptionalIdx);
8700 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
8708 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8711 for (unsigned E = Operands.size(); I != E; ++I) {
8712 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8726 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8730 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8734 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8738 void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
8746 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8749 for (unsigned E = Operands.size(); I != E; ++I) {
8750 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8760 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClamp);
8764 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
8766 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);
8798 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
8805 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8808 for (unsigned E = Operands.size(); I != E; ++I) {
8809 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8822 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8827 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8831 addOptionalImmOperand(Inst, Operands, OptionalIdx,
8848 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
8850 cvtVOP3(Inst, Operands, OptionalIdx);
8853 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
8886 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyBitOp3);
8894 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
8900 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,
8906 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);
8910 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
8973 void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
8975 cvtVOP3(Inst, Operands, OptIdx);
8976 cvtVOP3P(Inst, Operands, OptIdx);
8979 static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands,
8982 ((AMDGPUOperand &)*Operands[i]).addRegOrImmWithFPInputModsOperands(Inst, 2);
8984 ((AMDGPUOperand &)*Operands[i]).addRegOperands(Inst, 1);
8987 void AMDGPUAsmParser::cvtSWMMAC(MCInst &Inst, const OperandVector &Operands) {
8990 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1);
8991 addSrcModifiersAndSrc(Inst, Operands, 2, Opc, AMDGPU::OpName::src0_modifiers);
8992 addSrcModifiersAndSrc(Inst, Operands, 3, Opc, AMDGPU::OpName::src1_modifiers);
8993 ((AMDGPUOperand &)*Operands[1]).addRegOperands(Inst, 1); // srcTiedDef
8994 ((AMDGPUOperand &)*Operands[4]).addRegOperands(Inst, 1); // src2
8997 for (unsigned i = 5; i < Operands.size(); ++i) {
8998 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
9003 addOptionalImmOperand(Inst, Operands, OptIdx,
9007 addOptionalImmOperand(Inst, Operands, OptIdx,
9011 addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyClamp);
9013 cvtVOP3P(Inst, Operands, OptIdx);
9020 ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {
9028 Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));
9032 Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));
9041 void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {
9043 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);
9155 ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {
9169 Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,
9178 ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
9209 Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));
9215 const OperandVector &Operands) {
9316 ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
9320 !isSupportedDPPCtrl(getTokenStr(), Operands))
9346 Operands.push_back(
9351 void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
9368 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
9372 for (unsigned E = Operands.size(); I != E; ++I) {
9410 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
9430 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9434 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9438 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
9441 cvtVOP3P(Inst, Operands, OptionalIdx);
9443 cvtVOP3OpSel(Inst, Operands, OptionalIdx);
9445 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
9449 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);
9453 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);
9454 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
9455 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
9456 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
9459 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9464 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
9470 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
9474 for (unsigned E = Operands.size(); I != E; ++I) {
9482 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
9522 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
9523 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
9524 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
9526 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9536 ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
9540 Operands, Prefix,
9545 ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
9547 Operands, "dst_unused", {"UNUSED_PAD", "UNUSED_SEXT", "UNUSED_PRESERVE"},
9551 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
9552 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
9555 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
9556 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
9559 void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
9560 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);
9563 void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
9564 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);
9567 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
9568 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());
9571 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
9584 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
9587 for (unsigned E = Operands.size(); I != E; ++I) {
9588 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
9625 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9629 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9633 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9637 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9641 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9645 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9649 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
9651 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);
9652 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);
9653 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9654 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
9659 addOptionalImmOperand(Inst, Operands, OptionalIdx,
9661 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
9662 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
9693 ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,
9697 return parseTokenOp("addr64", Operands);
9699 return parseTokenOp("done", Operands);
9701 return parseTokenOp("idxen", Operands);
9703 return parseTokenOp("lds", Operands);
9705 return parseTokenOp("offen", Operands);
9707 return parseTokenOp("off", Operands);
9709 return parseTokenOp("row_en", Operands);
9711 return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);
9713 return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
9715 return tryCustomParseOperand(Operands, MCK);
9781 ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {
9793 Operands.push_back(