Lines Matching defs:IDLoc

1606   bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1762 bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1774 bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
1775 bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
1795 const SMLoc &IDLoc);
1810 bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
3896 const SMLoc &IDLoc) {
3939 Error(IDLoc, Twine("image data size does not match ") + Modifiers);
3944 const SMLoc &IDLoc) {
3970 Error(IDLoc, "image address size does not match a16");
4008 Error(IDLoc, "image address size does not match dim and a16");
4997 const SMLoc &IDLoc) {
5016 Error(IDLoc, "invalid cache policy for SMEM instruction");
5040 Error(IDLoc, isGFX940() ? "instruction must use sc0"
5129 const SMLoc &IDLoc,
5179 Error(IDLoc, "missing dim operand");
5187 if (!validateMIMGDataSize(Inst, IDLoc)) {
5190 if (!validateMIMGAddrSize(Inst, IDLoc))
5217 if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
5222 Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]
5229 Error(IDLoc,
5242 Error(IDLoc, "ABS not allowed in VOP3B instructions");
5280 const SMLoc &IDLoc) {
5295 return Error(IDLoc,
5311 return Error(IDLoc, "instruction requires wavesize=32");
5316 return Error(IDLoc, "instruction not supported on this GPU");
5321 return Error(IDLoc, "invalid instruction" + Suggestion);
5335 bool AMDGPUAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
5361 if (!validateInstruction(Inst, IDLoc, Operands)) {
5364 Inst.setLoc(IDLoc);
5370 if (checkUnsupportedInstruction(Mnemo, IDLoc)) {
5380 return Error(IDLoc, "operands are not valid for this GPU or mode");
5383 SMLoc ErrorLoc = IDLoc;
5386 return Error(IDLoc, "too few operands for instruction");
5390 ErrorLoc = IDLoc;